High frequency clock generator on TIOA1?

[SupArdu]

I want to use Due Timer Counter to generate high frequency on TIOA1 which is PA2 or Due pin A7. TIOA1 is on TC0 channel 1, peripheral A, ID=28.
The code to achieve this is:

PMC->PMC_PCER0 = PMC_PCER0_PID28;   // clock enable TC1 with ID=28
  PIOA->PIO_ABSR &= !PIO_ABSR_P2;     // multiplexer pin PA2  to peripheral A for TIOA1
  PIOA->PIO_PDR = PIO_PDR_P2;         // deactivate GPIO on Pin PA2 (TIOA1) 

  TC0->TC_CHANNEL[1].TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVE | 
                              TC_CMR_WAVSEL_UP_RC | TC_CMR_ACPC_TOGGLE;
  TC0->TC_CHANNEL[1].TC_RC = 1;      // max. frequency
  TC0->TC_CHANNEL[1].TC_CCR = TC_CCR_CLKEN;

There is no clock at all on Pin A7 (measued with an oscilloscope).

What is missing?

[SupArdu]

I found the missing part:
It is necessary to trigger the counter. I do it by SW. The last line of my sketch needs to be:

TC0->TC_CHANNEL[1].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;  // clock enable, start

With TC_CMR_ACPC_TOGGLE, i.e. on RC compare toggle TIOA, the value of RC defines the frequency f=21/RC MHz.

With a slight modification there is a better choice of frequency:

TC0->TC_CHANNEL[1].TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |  // MCK/2 = 42 MHz
                              TC_CMR_WAVE |                 // Wavemode
                              TC_CMR_WAVSEL_UP_RC |         // cnt up, RC compare triggers
                              TC_CMR_ACPA_SET |             // RA compare sets TIOA to high
                              TC_CMR_ACPC_CLEAR |           // RC compare sets TIOA to low
                              TC_CMR_ASWTRG_CLEAR;          // SW trigger sets TIOA to low
  TC0->TC_CHANNEL[1].TC_RA = 1;
  TC0->TC_CHANNEL[1].TC_RC = 2;
  TC0->TC_CHANNEL[1].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;  // clock enable, start

Now RA compare sets TIOA to high and RC compare sets it to low and the frequency is f=42/RC Mhz.
The value of RA defines the duty cycle.