Christo:
I'm trying to understand what the delay will do to the ADC process, but my understanding of the manual isn't great. I've reread the manual on ADC several times but I cannot make sense of statements such as:An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Does this imply that the ADC circuit starts charging once a channel is selected in ADMUX but before the ADCSRA ADSC bit is set?
Yes. When no conversion us in progress, the sample capacitor is connected to the input channel pin selected by the mux.
Christo:
Elsewhere the manual states that the sample & hold of a channel only starts after the ADSC bit in ADCSRA is set, so a delay before setting ADCSRA shouldn't affect the charging of the ADC cap?
As far as I can tell, "sample and hold" comprises waiting 1.5 ADC clocks, then disconnecting the capacitor from the selected input pin and connecting it to the converter. I have found that a delay (between setting the mux and starting the conversion) of about one microsecond per 10K source resistance is needed to achieve accurate results. There is some delay built in to the sample process already, so no delay is needed when the source resistance is 10K or less (as recommended in the datasheet).