Got it figured out. Unfortunately, had some sneaking suspicions that may have just been confirmed about this GIGA R1 board, hence the anxiety of wanting to get this done. If someone could convince me otherwise, I would be very grateful.
Anyways...just needed some delay() to get er started.
void setup() {
Serial.begin(9600);
delay(4000);
Serial.println("test");
delay(1000);
Serial.println(RCC->BDCR, BIN);
}
void loop() {}
And the spew...
12:05:19.830 -> test
12:05:20.874 -> 1000000101100001
Everything looks as should except bit 6 set a flag.
Bit 6 LSECSSD: LSE clock security system failure detection
Set by hardware to indicate when a failure has been detected by the Clock Security System on the
external 32 kHz oscillator.
0: No failure detected on 32 kHz oscillator (default after backup domain reset)
1: Failure detected on 32 kHz oscillator
Of other concern is bit 1, LSERDY, as it was not toggled by hardware, and am unfamiliar with allowing "6 cycles of lse_ck" in order to poll that bit again.
Bit 1 LSERDY: LSE oscillator ready
Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck
clock to fall down after LSEON has been set to ’0’.
0: LSE oscillator not ready (default after backup domain reset)
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enabled
Set and reset by software.
0: LSE oscillator OFF (default after backup domain reset)
1: LSE oscillator ON
Well, that's my deal. Think I can close this as SOLVED for time being.