how to clear buffer for writeAckPayload

Hi, using the nrf2 examples were great! I just need to make a small change. The writeAckPayload, from what I have learned, writes to a buffer and is then FIFO'd out. Is there any way to clear the buffer?

if I for example
writeAckPayload(1,size);
writeAckPayload(2,size);
writeAckPayload(3,size);
each time I send data from my transmitter I get the data back, first second, third.

I have a requirement where I want to clear it all.
writeAckPayload(1,size);
writeAckPayload(2,size);
writeAckPayload(3,size);
clearBuffer();
writeAckPayload(8,size);
and hope to get back the 8 on my first send.

Does this make sense? I tried using flush_tx() and it is sort of working but wondering if that is not what that is for.

You should use .flush() command.

Why are you writing more than once to the ackPayload buffer between calls from the master?

Have a look at the second example in this Simple nRF24L01+ Tutorial

...R

I'm wring more then once to debug my issue. Each time I do that it buffers it. It is not my intention to do this, just illustrating the issue. I would have expected consecutive writes to over right the payload data but it puts it in a fifo que.

ArnavPawarAA flush is not available?
https://tmrh20.github.io/RF24/classRF24.html

https://tmrh20.github.io/RF24/classRF24.html

uint8_t RF24::flush_tx()

ulaoulao:
I'm wring more then once to debug my issue.

You seem to be adding bugs rather than finding them.

When there is a problem simplify the code as much as possible.

...R

Maybe I can explain it another way.

writeAckPayload(1,size); will set the payload with 1 byte. I get get that byte byt sending from the transmitter and receiving back ack.

If however something goes wrong, then I must somehow get that byte or it stays in the que. If all run well, no that will not occur.

take the following example.

Transmitter send 0x01 to get the current count form the receiver.

rx starts by setting payload to a 1.
tx - sends 1, gets a 1.
rx count up.
tx - sends 1, gets a 2.
rx count up.
tx - sends 1, gets a 3.

and that works. but here is the case example where it fails.

rx starts by setting payload to a 1.
tx - sends 1, gets a 1.
rx count up.
tx - sends 1, but something when wrong.
rx count up.
tx - sends 1, gets a 2.

if you add up the counts it should not have sent a 2, it should have sent a 3. Since the 2 was never ready out of the FIFO it seems to remain in there. I can do another tx send and get the 3. So I’m asking if there is a way to do this.

rx starts by setting payload to a 1.
tx - sends 1, gets a 1.
rx clears fifo and count up.
tx - sends 1, but something when wrong.
rx clears fifo and count up.
tx - sends 1, gets a 3.

That way I always get what I’m expecting. I’m simply asking is there a way to clear the fifo. That’s all, my reasons are for my own.

As I mentioned the examples work perfectly as they were intended. Code is simple and does its job. I have expand on it and I’m just asking if there is exiting functionally to clear out the fifo. I guess I can use the SPI incorrectly if there is not.

Whandall:
https://tmrh20.github.io/RF24/classRF24.html

uint8_t RF24::flush_tx()

See first post - " I tried using flush_tx() and it is sort of working but wondering if that is not what that is for. "
Yes that did help for the immediate flush but its not working %100. So I was questioning if that was the intended purpose.

ulaoulao:
If however something goes wrong,

What goes wrong?

Have you tried the code in my examples - I don't recall ever having the problem you describe.

...R