how to clear the interrupt[0,1] registers before re-enabling them?

This is probably stupid, but I'm having a small issue figuring out how to correctly apply attachInterrupt() and detachInterrupt()..

My code is simple, enableInterrupt(), in ISR, set volatile variable, disable interrupts, reset a timer, exit ISR.

attachInterrupt(LANE1, lane1gate, RISING);
...
void lane1gate() 
  {
    lanetrigger[0] = true;
    detachInterrupt(LANE1);
    detachtimer[0] = millis();
  }
...
if (millis() - lanetime[LANE1] >= INT_BLANK)
  {
     attachInterrupt(LANE1, lane1gate, RISING);
  }

After timer expires, re-enableInterrupt().

My problem is this: if something has triggered the interrupt pin while interrupts are disabled, it REMEMBERS that in a register someplace, so if this condition happens, when I re-enable the interrupt, it immediately and FALSELY executes the ISR.

Is there a way to prevent this? I suspect I could code around it and never disable interrupts, but that's what I remember from (old) school, so it's the first model I attempted..

Code on ATMega328 based free-duino, using interrupts 0 and 1, both have same effect.

I'm sure stupid-ish newby question, but if someone has a clue, I'd appreciate a pointer!!

I did actually search the forum and I found clues that seem VERY similar, but the code examples were pretty cryptic, so I couldn't quite figure out how to apply the information.. I'm GUESSING build a variable with the right bitmask then write that someplace before re-enabling interrupts.. I can probably figure that out if someone can point me to the right RTFM reference and what register is holding int[0,1] states..

Thanks so very much, all!!

-ET-

See this page:

http://gammon.com.au/interrupts

Scroll down to "clear flag for interrupt 0".

In short, this will do it:

EIFR = _BV (INTF0);  // clear flag for interrupt 0
EIFR = _BV (INTF1);  // clear flag for interrupt 1

Perfect! I feel so good having at least guessed I was seeing completely normal behavior:

Interrupts events (that is, noticing the event) can occur at any time, and most are remembered by setting an "interrupt event" flag inside the processor. If interrupts are disabled, then that interrupt will be handled when they are enabled again, in priority order.

SUPER tutorial/RTFM!! Thanks SOO much for the reference!

-ET-