I am using pro mini 16mHz.
The goal is to sample analogue sensor input at 8ksps (using faster pre-scaler ADC) for 0.1 sec once a second and loop those samples out continuously for one second, before getting new samples.
I have checked with short sketches that there is enough DRAM for an array buffer, with working memory still sufficient for additional variables, function calls and stability. Also sampling and sending (no input dummy values)buffer output on SPI.
I chose this chip because it shifts quantizisation noise above audio frequencies. It is also an extremely cheap experiment.
The L3 mode options would be hard-wired, L3 interface not needed.
However, I can’t see how to comply with the datasheet on latching data for the left/right channels.
If I am bit-banging a pin for WS, after sending each batch of two data bytes, the BCK(SPI CLK) is no longer at the right place?
Do I need a custom SPI to do this in sync, BCK and DATAI(MOSI) with 50% duty cycle WS?
Are the timing diagrams not going in direction left to right across page, but first data received is on the right-hand side?
But then WS transition is not occuring on falling edge of BCK.
As per the note on page 5,
‘Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
uda1330atsfilterdac.pdf (123 KB)