Hello. I am trying to use an ATmega32U4 based board (Arduino micro) to make a device that reports data over USB with the minimum possible latency. To do that, I would like to perceive when the bank becomes free, and ideally I would like to do so without polling.
I have two goals for getting the transfer timings:
1/ Queue data right before I will need to send it / know when I will not be able to accumulate more data before providing the transfer content.
2/ Notice that the host failed to ask for data at the previous USB frame, and send different data as a result. (Not just clear the bank before writing every time)
From the datasheet, I believe I should be able to use an EPINTx interrupt routine to do this, with TXINE set. But I can't find the syntax anywhere. For timers for example, it's ISR(TIMERx_COMPA_vect), so I assume it must be a variation of this, but I haven't found any mention of it anywhere.
If that's correct, could someone give me the syntax / even better, point me to where I could've found it ?
If not(/if I'm going to break everything by defining my own ISR), how comes ? Are there other options ?