Hello,
I'm intended to use a SIM7080G module on a custom board. My problem is, that I've never done LGA chip design, and I'm stuck at the bottom side connections, especially the GND.
So I have the footprint in KiCad:
First of all, how should I connect the "big" GND pads (3,1x2,6mm) in a two layer design? (the bottom side is GND copper zone)
I could only think of via in pads, the manufacturer seems to be able to handle it (JLCPCB)
But how many via should I place in them?
Thanks in advance.
I just found some more info, that the filled and capped via holes should not be over 0,5mm.
I don't think that making a via in pads is a good idea since the vias usually rise slightly above the plane and them prevents the chip to hold its place.
Why not route the track from GND pads outside the chip on upper left corner of the footprint?
Are the ground pads used for thermal reasons?
Are the pads solder mask defined or non-solder mask defined?
Will JLCPCB use the solderpaste stencil you provide?
As @belmont1591 showed with his pictures, and as the above links shows, it can be done with filled and capped vias, also available for proto boards.
The main disadvantage is the price. 
I don't think they are, it's a relatively low power NB-IoT chip. I think they help to make effective grounding in RF application.
I'm quite new to this kind of stuff, but the solder paste is not all over the pads:
Good question. I'll check it out. But with the capped vias it could work either way, right?
Filled and capped:
No
Many places will just use the pads or your soldermask as your paste mask and that may be too much paste for an LGA, so they should use your paste mask.
If you can afford it copper filled vias would be best but if you are sure these are not for thermal purposes then just plain epoxy filled via would be OK.
I don't know the size of your foorprint or what current goes through those GND pads so I can't say how many vias you will need.
Ahh okay, I see what you mean. I'll contact their support for the answer.
The GND pads are about 3,1x2,6mm. As JLCPCB stated, the filled via holes must be 0,5mm at most. I think I'll go with four 0,8/0,4mm vias distributed evenly. The peak current is approx 0,5A, and the average consumption is max. 200mA.
Sounds good!
I just got the answer, they will use this custom paste mask.
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