Looks OK to me apart from the following:
- Values of C4 C5 R6 are wrong, see my original sketch (100 by itself means 100 ohms, and nF means nanoFarads)
- The + input of the comparator needs to be biased to half VCC, so you need to add a 10K resistor between it and ground.
- You only want a sufficient frequency capture rang to cover the transmission frequencies (e.g. 185KHz to 215KHz), so you should add a resistor (or resistor + pot in series, so you can trim the centre frequency) between pin 12 of the PLL and ground. Then recalculate R9 C9. See page 15 of http://www.ti.com/lit/an/scha002a/scha002a.pdf.
- R13 is probably too large, you may need a lower value for better noise immunity, especially as reducing the frequency range of the VCO will increase the PLL demod output signal.
Also, what baud rate are you planning to use? The lower the baud rate, the less you will be affected by multipath interference. But the FTDI chip only goes down to 183 baud according to the datasheet I found, and I don't know whether the virtual COM port driver for the PC can even go that low. If you find that you need to use a lower baud rate, you will need to use an Arduino or something else to receive and retransmit the signal.
Do you have an oscilloscope? I wouldn't want to try getting this to work without one.
Good luck!