void setup()
{
// Set up the generic clock (GCLK7) to clock timer TCC0
GCLK->GENCTRL[7].reg = GCLK_GENCTRL_DIV(48) | // Divide the 48MHz clock source by divisor 48: 48MHz/48 = 1MHz
GCLK_GENCTRL_IDC | // Set the duty cycle to 50/50 HIGH/LOW
GCLK_GENCTRL_GENEN | // Enable GCLK7
GCLK_GENCTRL_SRC_DFLL; // Select 48MHz DFLL clock source
//GCLK_GENCTRL_SRC_DPLL1; // Select 100MHz DPLL clock source
//GCLK_GENCTRL_SRC_DPLL0; // Select 120MHz DPLL clock source
while (GCLK->SYNCBUSY.bit.GENCTRL7); // Wait for synchronization
GCLK->GENCTRL[1].reg = GCLK_GENCTRL_DIV(1) | // Divide the 48MHz clock source by divisor 48: 48MHz/48 = 1MHz
GCLK_GENCTRL_IDC | // Set the duty cycle to 50/50 HIGH/LOW
GCLK_GENCTRL_GENEN | // Enable GCLK7
GCLK_GENCTRL_SRC_DFLL; // Select 48MHz DFLL clock source
while (GCLK->SYNCBUSY.bit.GENCTRL7);
GCLK->PCHCTRL[25].reg = GCLK_PCHCTRL_CHEN | // Enable the TCC0 peripheral channel
GCLK_PCHCTRL_GEN_GCLK7; // Connect generic clock 7 to TCC0
GCLK->PCHCTRL[38].reg = GCLK_PCHCTRL_CHEN | // Enable the TCC4 peripheral channel
GCLK_PCHCTRL_GEN_GCLK7; // Connect generic clock 7 to TCC4
GCLK->PCHCTRL[11].reg = GCLK_PCHCTRL_CHEN | // Enable the EVSYS0 peripheral channel
GCLK_PCHCTRL_GEN_GCLK1; // Connect generic clock 1 to EVSYS
// Enable the peripheral multiplexer on pin D13(PORT_PA16)
PORT->Group[g_APinDescription[13].ulPort].PINCFG[g_APinDescription[13].ulPin].bit.PMUXEN = 1;
PORT->Group[g_APinDescription[13].ulPort].PMUX[g_APinDescription[13].ulPin >> 1].reg |= PORT_PMUX_PMUXE(6);
PORT->Group[g_APinDescription[6].ulPort].PINCFG[g_APinDescription[6].ulPin].bit.PMUXEN = 1;
PORT->Group[g_APinDescription[6].ulPort].PMUX[g_APinDescription[6].ulPin >> 1].reg |= PORT_PMUX_PMUXO(0xF);
// Event System /////////////////////////////////////////////////////////////////////////////////////////
MCLK->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; // Switch on the event system peripheral
// Select the event system user on channel 0 (USER number = channel number + 1)
EVSYS->USER[EVSYS_ID_USER_TCC0_EV_0].reg = EVSYS_USER_CHANNEL(1); // Set the event user (receiver) as timer TCC0 //EVSYS_ID_GEN_TCC0_TRG
// Select the event system generator on channel 0
EVSYS->Channel[0].CHANNEL.reg = EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT | // No event edge detection
EVSYS_CHANNEL_PATH_ASYNCHRONOUS | // Set event path as asynchronous
EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TCC4_OVF); // Set event generator (sender) as external TCC4_OVF
TCC4->EVCTRL.reg = TCC_EVCTRL_OVFEO; //Overflow/Underflow Output Event Enable
TCC0->EVCTRL.reg = //TCC_EVCTRL_TCEI1 | // Enable the TCC event 1 input
TCC_EVCTRL_TCEI0 | // Enable the TCC event 0 input
//TCC_EVCTRL_TCINV1 | // Invert the event 1 input
//TCC_EVCTRL_TCINV0 | // Invert the event 0 input
TCC_EVCTRL_EVACT0_RETRIGGER; // Set event 0 to count the incoming events
// TCC0 /////////////////////////////////////////////////////////////////////////////////////////
TCC0->CTRLA.reg = TC_CTRLA_PRESCALER_DIV1024 | // Set prescaler to 1024, 1MHz/1024 = 976Hz
TC_CTRLA_PRESCSYNC_PRESC; // Set the reset/reload to trigger on prescaler clock
TCC0->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; // Enable oneshot operation
//TCC_CTRLBSET_DIR; // For timer/counter is counting down (decrementing)
while (TCC0->SYNCBUSY.bit.CTRLB); // Wait for synchronization
//TCC0->DRVCTRL.reg = TCC_DRVCTRL_INVEN4; // Invert the output to generate an active low pulse on TCC0/WO[4]
TCC0->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM; // Set-up TCC0 timer for Normal (single slope) PWM mode (NPWM)
while (TCC0->SYNCBUSY.bit.WAVE) // Wait for synchronization
TCC0->PER.reg = 976; // Set-up the PER (period) register 1Hz PWM
while (TCC0->SYNCBUSY.bit.PER); // Wait for synchronization
TCC0->CC[4].reg = 488; // Set-up the CC (counter compare), channel 0 register for 50% duty-cycle
while (TCC0->SYNCBUSY.bit.CC4); // Wait for synchronization
TCC0->CTRLA.bit.ENABLE = 1; // Enable timer TCC0
while (TCC0->SYNCBUSY.bit.ENABLE); // Wait for synchronization
// TCC4 /////////////////////////////////////////////////////////////////////////////////////////
TCC4->CTRLA.reg = TC_CTRLA_PRESCALER_DIV1024 | // Set prescaler to 1024, 1MHz/1024 = 976Hz
TC_CTRLA_PRESCSYNC_PRESC; // Set the reset/reload to trigger on prescaler clock
//TCC4->DRVCTRL.reg = TCC_DRVCTRL_INVEN4; // Invert the output to generate an active low pulse on TCC0/WO[4]
TCC4->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM; // Set-up TCC0 timer for Normal (single slope) PWM mode (NPWM)
while (TCC0->SYNCBUSY.bit.WAVE) // Wait for synchronization
TCC4->PER.reg = 5000; //976; // Set-up the PER (period) register 1Hz PWM
while (TCC0->SYNCBUSY.bit.PER); // Wait for synchronization
TCC4->CC[1].reg = 3000; //488; // Set-up the CC (counter compare), channel 0 register for 50% duty-cycle
while (TCC0->SYNCBUSY.bit.CC4); // Wait for synchronization
TCC4->CTRLA.bit.ENABLE = 1; // Enable timer TCC0
while (TCC0->SYNCBUSY.bit.ENABLE); // Wait for synchronization
}
void loop() {}
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