Hi,
I'm interfacing to a device that performs a MR. It's DMA engine wants to read between 48~1024 bytes from my UNO as an ST.
Problem is, the twi_onSlaveTransmit function is only called on the first arbitration, and then expect the master to listen for an ACK if there is more data in the buffer.
Which means there's a 32 byte limit without the master starting another READ TO ADDR cycle.
The proprietary hardware I'm interfacing to does not want to interrupt every 32 bytes and wants to DMA 1024 bytes (or 48 bytes or 512, etc).
Judging by the UNO twi implementation, this looks impossible.
What I don't follow is, during a slave transmit, who drives ACK? Does the master ACK until it is satisfied, or does the slave need to know how much data to send beforehand so it can continue to fill the buffer until (which also requires tweaking the stack).
I think I'm missing something important here that isn't in the ATMega datasheet, nor is it clearly defined on the i2c-bus.org pages.
Advice?
Thanks
PT