I'm trying to take the VidorGraphics logo sample and make a simple test pattern generator with a small frame counter on the HDMI output. To tune the timing to update 60 fps I'm toggling an output pin around my main 'render' loop that I can watch on a scope and adjust delays in my design as needed. This seems to be working, but the image flickers. I assume this is because my render loop isn't tied in any way to the actual vertical interval of the HDMI output.
Is it possible to somehow tie my screen refresh actions to the actual video vertical interval, and is it reasonable to assume that doing so would allow me to make a solid refresh counter? Maybe an interrupt coming off of the FPGA?
hi, yes, it would be possible but i guess there are some caveats. at the moment jtag access is a bit slow as it's mostly bitbanged. we're planning to optimize it but until then interaction with the FPGA is going to be a bit slow and probably that would limit your ability to perform the generator with frame counter you're looking at.
to avoid flickering the other possibility (which is adviceable) is to have double buffering which has also been suggested elsewhere. this is something that for sure will come sooner.
Thanks, that makes good sense. I agree the double buffering support would be a great add for most applications. In this test pattern generator that I'm making that is showing a frame-accurate counter I think double buffering might cause frames to be repeated (by design), and I'd probably still want to somehow be locked to the vertical interval of the video signal.
Do you think it's more possible for the FPGA could toggle a physical pin upon the vertical interval of the video output, and that I could wire it to a pin that I can interrupt on from the Arduino software?
We don't need physical ISR that hard wire to the hardware but we can implement ISRs in the arduino code that continuously read the ISR block in FPGA (Periodically or Asynchronous).
The normal arduino has setup() and loop().
Maybe we could add up VidorISR_HDMIRetrace(); or we can create some logic core in FPGA that can carry multi-channel ISRs and trigger the VidorISR_XXX();. (non realtime ISR)