int type binary storage, LSB first?

Hey guys, i have this piece of code

struct
{
char msgHeader;
signed int data[3];
char star;
byte CS;
} msg;

msg.msgHeader = ‘S’;
msg.star = ‘*’;
msg_size = sizeof(msg);

msg.data[0] = 1;
msg.data[1] = 2;
msg.data[2] = 400;
msg.CS = 0;

byte p = (byte)&msg;

for (int i = 0; i < msg_size - 2; i++)
{
msg.CS ^= (byte)p*;*
}
Serial.write(p, msg_size);
The output i get over serial ( in hex mode)
53 01 00 02 00 90 01 2A C1
Notice that the output is low byte then high byte of each variable. Why is this?
I am running out of cycles on this uC, and fast ways to fix this?
Thanks.

well, i changed it to this

msg.data[0] = ((distance_moved << 8) | ((unsigned int)distance_moved >>8)) ;
msg.data[1] = ((voltage << 8) | ((unsigned int)voltage >>8)) ;
msg.data[2] = ((current << 8) | ((unsigned int)current >>8)) ;

to get it to send the high byte first. Is there a better way to fix it, and why does it store int’s like that?

http://en.wikipedia.org/wiki/Endianness

Why does the byte-order matter?

Well, learned something new today.

It matters because 1 (int) variable consists of two bytes, and i am trying to have two uC pass variables back and forth, and i could run into a problem if on uC expects MSB first but gets LSB. So therfore either way doesn't matter, as long as they both agree on the method.

I had already planed out my comm scheme to be MSB first, and wrote that into the other uC; because well, that just made the most sense to me.

Why does the byte-order matter?

It matters when you have some sort of communications between systems that (might) use different byte orders ("binary" files, networking or other comm link, shared memory, and on 8-bit processors like AVR, perhaps shared data between different languages (asm and C, for example.))

See Internet Experiment Note 137 "On Holy Wars and a Plea for Peace": http://www.ietf.org/rfc/ien/ien137.txt

In (somewhat modern) CPUs, most Intel architectures (x86) and chips are "little-endian" (low bytes in low addresses), and most motorola (now Freescale) chips (68xxx) were big-endian. Some CPUs (PPC, MIPS, ARM) can do either one (sometimes based on chip configuration, sometimes based on smaller config (per-process or memory region.))

Most people will not need to pay any attention.