Another member pointed out to me that, as you've placed them, the resistors form a voltage divider, R2 >> R3 notwithstanding.
He suggested that I change the arrangement slightly, as attached. I could not argue.
Guess I'd always implemented the divider reflexively.
The low-? resistor still limits the in-rush but without a voltage divider effect which diminishes VGS.
In the context of these "logic-level" MOSFets, you want to get as much of that logic-level output applied to the gate as you can. (This especially if a much lower value of R2, to accomodate faster switching, were used.)
