IUE:
I am developing a mobile robot using Arduino Mega and I am going to use two AS5147P magnetic encoders to get wheel positions to develop a PID controller for robot.
I need to know is it possible to connect these two encoders to an Arduino mega via SPI Interface to get the wheel position at the same time?
It is possible; but, one after after what we call sequential. When the sampling is fast enough, it is usually termed as simultaneous/concurrent though (in the strict sense) they have different meanings.
pylon:
The answer is yes, although to be exact "at the same time" is never possible in a single core von Neumann architecture CPU.
Is ATmega328P a 'von Neumann architecture CPU' or 'non von Neumann architecture CPU'; where, the later has no capability to execute user program out of RAM?
Then it would be possible to add external RAM with ATmega328P, store/download application program into this RAM area and then instruct the MCU to begin program execution from a RAM address -- is it this that you want to say?
In 80x86, there are instructions to load the PC (Program Counter) with the address of the application program stored in RAM. In 8051, there are also similar instructions. In ATmega328P , are there similar instructions? If not, how can we say that ATmega328P is a von neumann computer?
Then it would be possible to add external RAM with ATmega328P, store/download application program into this RAM area and then instruct the MCU to begin program execution from a RAM address -- is it this that you want to say?
No.
In 80x86, there are instructions to load the PC (Program Counter) with the address of the application program stored in RAM. In 8051, there are also similar instructions. In ATmega328P , are there similar instructions? If not, how can we say that ATmega328P is a von neumann computer?
Because the flash memory is a Random Access Memory as the term is used in the definition. The definition was made when Random Access Memory and tapes or punched paper tape was the two memories available. I cannot find any sentence in the definition that says there must be an instruction that loads the PC with an address, do you?
Because the flash memory is a Random Access Memory as the term is used in the definition. The definition was made when Random Access Memory and tapes or punched paper tape was the two memories available. I cannot find any sentence in the definition that says there must be an instruction that loads the PC with an address, do you?
To the best of my knowledge, there is no instruction for the ATmega328P to load its PC with an arbitrary address.
GolamMostafa:
Is ATmega328P a 'von Neumann architecture CPU' or 'non von Neumann architecture CPU'; where, the later has no capability to execute user program out of RAM?
From the Atmega 328 datasheet ...
"In order to maximize performance and parallelism, the AVR uses a Harvard architecture"
In 1945, John Von Neumann conceived an architecture for a Computing Machine (the Computer) in which 'executable codes (the program)' and 'non-executable data' will reside in 'one' memory space (ROM or RAM or ROM+RAM) whose every location can be addressed by the Program Counter. All computers including 8085, 6502, Z80, 80x86, 6802, ... are built based on this single space principle. It is the Intel 8751 in which we see that there are two separate memory spaces: 'ROM Space for Program' and 'RAM Space for Data'; the processor has been termed as 'non von neumann' architecture. However, 8751 could have been modified to work as 'von neumann' computer by conditioning 'PSEN and RD/' signals (Fig-1) to execute application program residing in the RAM space -- this is what is the 'stored program' concept of von neumann computer.
Figure-1: Schematic of a 8751 based Microcontroller Trainer
In ATmega328P Microcontroller, we have Program Memory and EEPROM Data Memory in separate address locations. The address/locations of the Program Memory are accessed by a 14-bit Program Counter; whereas, the locations of the EEPROM are accessed my EEADR Reisters. Let us deposit a small program in the EEPROM, but we will not be able to execute it as the PC has no access to EEPROM. Moreover, the ATmega328P is not equipped with 'Bus signals' like 8751 to allow us connecting external RAM and fetching instructions from it for execution. Therefore, ATmega328P is not a 'von neumann' computer.
TheMemberFormerlyKnownAsAWOL:
Fake it with a "push dummy PC" followed by a "return" instruction.
Figure-1: Flash, EEPROM, and SRAM spaces of ATmega38P
Yes! It is possible to fake the ATmega328P in respect of loading its PC with any address value of the flash and not of the EEPROM or SRAM as the PC always hits at the flash to fetch code-word and execute it.
ldi r16, 0xFF
out spl, r16
ldi r16, 0x08
out sph, r16 ; SP is loaded with 0x08FF
//----------------
ldi r16, 0x01 ; higher byte of the user program address
push r16
ldi r16, 0x23 ; lower byte of user program address
push r16 ; address 0123 is stored in STACK
//---------------
ret ; PC = 0x0123
The MCU will begin program execution from location 0x0123 of the flash (and not of EEPROM or SRAM); although, the same addresses are present in EEPROM and SRAM (Fig-1).
AVR also has IJMP and ICALL instructions that set the PC to the value in the Z register.
But even on the new Mega0/Tiny0/Tiny1 chips (which have a unified "data" address space), you can't get code to execute out of RAM...
westfw:
AVR also has IJMP and ICALL instructions that set the PC to the value in the Z register.
But even on the new Mega0/Tiny0/Tiny1 chips (which have a unified "data" address space), you can't get code to execute out of RAM...
But, you are not voting if ATmega328P is a von neumann computer or not?
TheMemberFormerlyKnownAsAWOL:
What do the One Fifty say?
That One Fifty has to understand first the difference between 'Instruction Read' and 'Opcode Fetch'; but, I am not sanguine if they have gone to that level of understanding.
Harvard. The instruction decode parts of the cpu are connected directly to the flash only.
It’s slightly “modified” in that the databus CAN access the program memory (via SPM or the unified address space)
I’m not sure what it means when an arm cm0 is described as modified Harvard, when apparent both instructions or,data can be accessed on the same address space. Perhaps it has something to do with the multiple buses and bus controllers.
