Dacha011:
@PaulRB - Thanks for sharing you view on I1 & I2 with me !@MarkT - "Almost all logic chips require all logic inputs and outputs to be within the range GND-0.3V and Vcc+0.3V at all times, powered up or not." - wooow, info like this are worth pure gold for a beginner like me. It saved me not only many hours of debugging and struggling to find out the problem, but probably it also saved many IC from being fried ! Thanks MarkT !
While you were told what is wrong, there hasn't been an explanation for why doing this is bad, so I'll give it my best shot here.
I've attached a diagram of how the output pins work for a certain chip. While all chips will have different logic attached to them, the key feature to pay attention to here are the two diodes next to the I/O pin marker. basically all digital chips you use will have a pair of these diodes on every pin. You may already know that diodes have a relatively constant amount of voltage drop no matter the current flowing through them. The pair of diodes on the pin provide a path for static to discharge into the chip without creating an obscene amount of voltage in the process.
The diodes are connected directly to the chip's power rails so that static discharge through them is dumped straight out of the chip instead of through the electronics. However, if the chips power is disconnected and you apply voltage to one of the other pins, the power can travel up the VDD diode and give power to the entire rest of the chip. If you have GND connected to another pin, the current from the circuitry can travel up the VSS diode and get out of the chip. This "phantom powers" the chip, and can be enough to allow partial operation.
There's some more discussion of it here on this Stack Exchange thread: Will cutting power to a CMOS chip effectively remove it from the circuit? - Electrical Engineering Stack Exchange