Issue:- Is it possible to lock up the ethernet chip on an Arduino Leonardo ETH so badly that even if the onboard watchdog resets the board, the ethernet chip will not reset? I think it is from past experience. The networking locked up after just a few days of internet facing duty.
I've been told that it can too. That the AVR’s onboard watchdog only resets the ATmega32U4 itself—it toggles the 32U4’s RESET line and re‐runs your sketch, but it does not toggle or power-cycle any external chips (like a W5500 Ethernet controller). If the Ethernet chip has gotten into a bad state (hung SPI, bus lock, internal FSM in a bad state), a WDT reset of the AVR alone won’t touch it—so it’ll stay hung even though the MCU is brand-new out of reset.
I've confirmed this arrangement from the reference schematic. EDIT - Correct schematic now used.
Solution offered:- A wiring hack to drive the Ethernet‐chip RTSn from a spare GPIO. At the top of setup() (before you touch SPI), assert the reset line (drive it LOW), delay 5–10 ms, then release it HIGH. This guarantees you start from a known-good state even if the module’s RTSn pin isn’t tied to the AVR’s RST.
Leonardo's GPIOs should be able to overdrive the 10k pull down resistor on the RTSn line without having to cut the track.
Is this valid as it's fiddly soldering? Or is there another alternative?
The reference circuit looks incorrect to me. RSTn is active LOW, so I would expect the 10k resistor on the RSTn pin to be a pull-up and connected to the 3.3V line, not a pull-down to ground.
The W5500 datasheet says that RSTn should be held down for at least 500uS so I would expect a 5ms delay to more than suffice.
A GPIO pin on the 32u4 can sink a maximum of 40mA of current, but the current across a 10k resistor at 3.3V is just 330uA (0.33mA) so it should have no problem holding down RSTn.
A pause of 500us is generally indiscernible to a human so I suppose you could just tie the 32u4 RESET to the W5500 RSTn, assuming there is a convenient way to do so, and save a GPIO pin. A firm positive press will more than likely reset both, but I guess the GPIO pin approach does give you a guaranteed duration.
The GPIO would probably work but what if it is in a high state and the reset is driven low by another source? I suggest a low VF diode for isolation. This will form the 'or' function driving the reset. You can also use a MOSFET as a diode if you like. At the lower current the forward drop of a diode will be less.
Shockley diodes will normally have lowest voltage drop. At about 200 mA voltage drops for common diodes are (from the internet): As the current rating goes up so will the size.
DIODE Vdrop @ 200 mA Diode type
1N4148 1.0 Signal
1N4007 0.8 General rectifier (1A)
1N5408 0.6 General rectifier (3A)
1N5817 0.25 Schottky (1A)
1N5820 0.2 Schottky (3A)
Hopefully this helps.
Mod edit: Rude comment removed.
This is the correct schematic from the Arduino website. I have learned something tonight. And yes as suggested, RSTN is pulled high via a 10k resistor, not low as I initially said. Sorry, I don't know where the other schematic came from.
But doesn't this still mean that I can over-drive it low via a GPIO pin to reset the W5500 chip?
P.S. Why is this not part of the design. What's the point of half of a watchdog? Just the back legs?
Yes but need the isolation as the reset button will short the GPIO if it is high. If it is isolated it will work just fine.
That is a very broad question with thousands of possible answers. As I see it the watchdog protects the CPU if it gets lost in the code. There were a few processors that drove the reset pin low, I believe Motorola was the first with that.
In my systems I have what I call PowerDog. I use a setup called a "PowerDog," which is essentially an advanced watchdog that cycles the system power. It works by powering down all the hardware, forcing a complete reset when the power is restored.
Here's how it works: The processor must respond within a specified time frame by sending acknowledgment pulses. If the processor is up and running, it keeps sending these pulses, preventing a power cycle. However, if the processor fails to respond, the PowerDog cycles the power again until the system comes back online. This signal is AC coupled to force the pin to cycle. The pulses are set high and low in different parts of the code, never in an interrupt.
The line used to pat the watch dog can be read at reset to determine if you are being reset by the dog or a power failure.
I designed this approach many years ago to address issues where internal watchdog timers only reset the processor but fail to reset external hardware.
You could possibly spend maybe the next 100 days looking up watchdog and its variations and not read them all.
1 Like
No it can't. That is the point where damage will be done to the Arduino and it is not even guaranteed to function.
I have a felling I have corrected you on this point before, but if not it is something you have to understand.
That's the specification for source current taken directly out of the 32u4 Datasheet and I was writing under the (possibly now erroneous) assumption that sink current capability would be the same as source current. Of course one would never push GPIO pins to that extent anyway. However, now that you mention it, I do have a vague recollection that someone might have mentioned quite some time ago that sink does not necessarily equal the source current despite what some references might say. If so then I stand corrected (maybe again).
What other source could drive pin RSTN? According to the (correct!) schematic, it's only connected to +3.3V via one 10k resistor (RN8B). There are no other connections. I’ve confirmed this by multi-meter. There is a direct short between the high side of RN8B and the +3.3V header pin.
Yes.
This question is in regard to the stage 1 (4 seconds) watchdog. The whole Leonardo board will be overseen by another shielded Arduino Nano feeding power via a 40A MOSFET. It’s sole aim will be to watch over the Leonardo and power cycle it if locked up. And also power cycle it every 6 hours notwithstanding.
It will also have it’s watchdog enabled for an 8 second period. That’s stage 2.
But presumably it can sink 0.33 mA? Page 384 of the datasheet says the pins can sink 20 mA (as tested) but more is likely.
Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
and it goes on to give limits for the entire port…
1 Like
Per the schematic linked to by the OP, I looked at it has a reset button. pushing that connects the Reset to ground any anything connected it. The diode forms an or and prevents the GPIO from being grounded with the reset button.
Let me show you what the data sheet says:-
Note where it says This is a stress rating only and also where it talks about operation at these values is not assured. So that means anything over 20mA.
That is correct.
But there are restrictions on groups of pins and port numbers.
1 Like
So the problem is the CAT811 chip located on the schematic at grid 8A? I see. It’s got push-pull drive, so it could be high (normal state) and then my hack tries to yank it low following a timeout. Bang!
Ponder on this I will…
Can I ask where you suggest placing the diode exactly?
Having pondered… From the datasheet:-
The CAT811 protects uPs against brownout failure.
Q. Can anyone see if RESET_W connects to anything else on the schematic? I can’t and I suspect that it’s only for the WIZnet chip as an abreviated RESET_WIZnet label.
- What if I removed CAT811? I can live without brownout failure are there are other steps I can take like more capacitors or a 5.5V super capacitor. That would also offer up a nice pad to solder the GPIO wire to.
- Similar to 1, but just cut the track, remove some resist and solder to that.
- Cut the RSTN pin, raise it and solder to that. A bit fiddlier.
Use a driver transistor on the GPIO line to forcefully yank RSTN low for 1 ms. That should be doable without blowing CAT811 up.
Any comments?
No, a super capacitor is right out, and other capacitors are not a replacement for an inadequate power supply.
No, once the reset is started, all the output revert back to being inputs before the minimum amount of time has expired for a proper reset.
No, I was the first to do it in 1976, the patents on this first appeared two years after I did it.
Of course I didn't come up with the name "watch dog" I called it an auto reset circuit.
I (G8HBR) was working on a 70cm ham radio repeater for Manchester north the time with a friend G4BVE who was also working on the Manchester South project. I told him about this circuit but he insisted that he would not need it because his code was robust.
Anyway, after four drives down a three mile unmade track in the first month, just to press the button, he soon adopted my circuit design.
1 Like
Why are (super) capacitors not suitable for preventing brown outs, whilst being suitable for overcoming power outages?
RE: transistor driver
Reversion to input is not a problem. Is there some confusion as to what I’m trying to reset? I’m trying to reset the WIZnet chip following a watchdog event. So it goes like this:-
- Watchdog timeout.
- CPU reset.
- GPIO pins all go input.
- delay (1000) in startup().
- GPIO pin set to output.
- Yank reset transistor low → short RESET_W to ground.
- delay (100) → only need 500 uS.
- GPIO pin goes high → RESET_W goes high.
- Restart networking in setup().
- Shinny?
Or am I still missing something please?
Not to upset you, but Voyager 1 has multiple watchdogs and these would have been designed many years before its 1977 launch 
Some time 1960s.
1 Like
