ISR Timer Firing for TC3

Official Hardware Classic Zero
1

I can't for the life of me see why the ISR isn't firing. I've wired TC3 to Generator #1 (32,768KHz) with a 1024 prescale and 32 count for a 1Hz interrupt, which isn't firing.

  PM->APBCMASK.bit.TC3_ = 1; 

  // select clock, enable, feed to peripherals
  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_TCC2_TC3 ;    // select
  GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_GEN_GCLK1 | GCLK_CLKCTRL_CLKEN;   // enable using generator #1
  while (GCLK->STATUS.bit.SYNCBUSY) { };                                        // Wait for general clock to be synced

  // timer 3 lcd screen
  TC3->COUNT8.PER.reg = 32U; // 1 sec
  TC3->COUNT8.DBGCTRL.reg = TC_DBGCTRL_DBGRUN;
  NVIC_SetPriority(TC3_IRQn, 3);
  NVIC_EnableIRQ(TC3_IRQn);
  TC3->COUNT8.INTENSET.bit.OVF = 1;
  TC3->COUNT8.CTRLA.reg = TC_CTRLA_MODE_COUNT8 | TC_CTRLA_RUNSTDBY | TC_CTRLA_PRESCALER_DIV1024;
  TC3->COUNT8.CTRLA.bit.ENABLE = 1;

    __enable_irq();

and

void TC3_Handler (void) {
  
  //events.lcdToggle = 1;
  //events.lcdUpdate = 1;

    adcPrintDisplay1Full();

  // END OF YOUR CODE
  TC3->COUNT8.INTFLAG.bit.OVF = 1; //Writing a 1 to INTFLAG.bit.MC0 clears the interrupt so that it will run again
}
2

Try enabling the OVF interrupt after setting MODE to COUNT8.

The SAMD21 datasheet[1] has this to say about initializing the counter:

30.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is disabled (CTRLA.ENABLE =0):
• Control A register (CTRLA), except the Run Standby (RUNSTDBY), Enable (ENABLE) andSoftware Reset (SWRST) bits

Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected" property in the register description. The following bits are enable-protected:
• Event Action bits in the Event Control register (EVCTRL.EVACT)

Before enabling the TC, the peripheral must be configured by the following steps:

  1. Enable the TC bus clock (CLK_TCx_APB).
  2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register(CTRLA.MODE). The default mode is 16-bit.
  3. Select one wave generation operation in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN).
  4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control Aregister (CTRLA.PRESCALER).
    – If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
  5. Select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register(CTRLBSET.ONESHOT).
  6. If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter Direction bit in the Control B register (CTRLBSET.DIR).
  7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN).
  8. If desired, enable inversion of the waveform output or IO pin input signal for individual channels via the Waveform Output Invert Enable bit group in the Control C register (CTRLC.INVEN).

[1] https://community.atmel.com/sites/default/files/forum_attachments/SAM-D21-Family-Datasheet-DS40001882B.pdf

3

That's got it. I've still to get used to setting id's and mode's in this manner. Thanks bud!