I am trying to make a bunch of devices access a single Real Time Clock module, so I can have 6 - 12 clocks snyc'ed to the same time...
I was originally thinking of just using the 1sec. pulse option, tying the pulse into a number of arduino on interrupt pins, and then updating seconds on each clock independently. while that works for a simple demo, I would need to do a bit more than that...
It'd be preferred to have each clock be able to call out to the DS-1307 and get the time back from it... Then possibly trigger the next arduino in line to request the time from the DS1307, with a digital out and an interrupt.
You can use a lot of Masters on the I2C bus, but it won't work in this situation. As soon as two Arduinos/ATmegas access the DS1307 at the same time, you are in trouble.
I think that the only good solution is to have some kind of one device as a central control unit that controls everything. It checks the time and controls the DS1307.
The other devices should get a signal from the central controller. It is possible with a serial connection, or a digital pin, or even with the I2C bus. I don't know if the broadcast is implemented in the Wire library yet, but that would be useful.
I have Digital Pins 4+7 available. I was thinking about parallelling the SCL & SDA lines from all the arduinos. And connecting Pin 4 to pin 7 on the next arduino.
I'd read the time with the first Arduino with the standard procedure.
Then I'd send Arduino # 1 pin 4 HIGH.
Arduino #2 pin 7 would see the High, and then read the clock module with the standard procedure.
then arduino#2 pin 4 would go HIGH.
Arduino #3 pin 7 would see the High, and then read the clock module with the standard procedure.
and so on...
If it works, this would probably be the easiest process, and would be fast too. Beyond that, I wouldn't have to
deal with any major additional circuitry, and it would be plug-n-play, with the ability to add in as many clocks as needed, while keeping them all (almost) in sync. I say almost in sync, as each arduino would be a few ticks behind the one before it...
In the Wire library, Wire.cpp and twi.c in the Wire/utilities folder are what make I2C work.
22.2 of the data sheet says
All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol.
22.4 says
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure
that transmissions will proceed as normal,even if two or more masters initiate a transmission at the same time.
Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the transmission. All other
masters should cease transmission when they discover that they have lost the selection process. This selection
process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should
immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that
multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data
being transferred on the bus must not be corrupted.
• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks
from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration
process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be
wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high
period. The low period of the combined clock is equal to the low period of the Master with the longest low period.
Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods
when the combined SCL line goes high or low, respectively.
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read
from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master
can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing
Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA
line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several
masters are trying to address the same Slave, arbitration will continue into the data packet.
I don't know if the files above support this or not.
GoolGaul, your solution would work, and also what I mentioned would work.
I think in the end it is the same amount of work.
I prefer a central control unit, and a digital trigger line that connects all. But that is only my personal preference, you should choose what suits you best.