Latching detector -- am I doing this right?

Other Hardware General Electronics
1

I have a protection circuit that will send a logic high to an output if things go "out of spec". The details aren't really important -- suffice it to say the detector works OK, but I'm trying to set up a latch (?) so that if/when things return to normal, the protection remains tripped until it is manually reset. In logic terms, if the input to the system is low, the output is low. If the input goes high, the output goes high. If the input returns to low, the output will remain high indefinitely. Only way out is a power cycle.

Because this is a protection circuit, I don't want to depend on software to handle this. I have two designs ("A" and "B" in the attached diagram) that simulate OK, but I have concerns...

Design "B" is simple -- there's an N-channel FET with 5V on the drain. The source is grounded through a 10K resistor, but between the source and resistor, there's a trace to the gate. The idea is that, once the transistor is turned on by the external input, it will keep itself turned on by its own output. I suspect that since the input and source pin are connected via diodes, it "floats" when there's no input (usually there would be a pull-down to ground.) I don't know if that's OK. Is it? Ideal FETs have infinite input impedance, so in theory they should be more or less immune to spurious noise. Can I count on that? If I ground it through a resistor, the output collapses and it turns off.

Design "A" is a fix to this, by isolating the feedback through a P-channel FET. AFAICT, this works nicely -- I can properly apply pull-ups and pull-downs, but the parts count goes up quite a bit, and I don't know if it's warranted. Maybe there's a better way...

Am I going about this all wrong? Is "latch" even the right term? The Wikipedia article had lots of extra stuff that doesn't apply to me: set/reset inputs, inverted outputs... Not sure if it can be scaled down, or if it then becomes something else entirely.

latch.png

2

Not sure I understand your fear of software. I'd be tempted to use something like an Attiny13 as an independent latch, if I really thought I needed such a thing. You can get them for under $2 and they can be programmed to behave whatever way you like. Being independent from the main controller would ensure it will still work if the main controller trips over it's own software. To me it would be a lot simpler, cheaper and more reliable than a small box full of MOSFETS, diodes and resistors.

3

Ideal FETs have infinite input impedance, so in theory they should be more or less immune to spurious noise.

Two issues, on the opposite side:

  1. fets typically have higher Vgs, making them more immune to noise - noise needs to reach a higher level to turn on a fet.
  2. fets have infinite dc input impedance. So a high-impedance source can create sufficient Vgs to turn them on.

If you are concerned about noise, you should use a small resistor (in parallel with g-s) to reduce the fet's input impedance.

Your A will work and B will not.

Now, what you are looking for is essentially a SCR. You can get a scr, or build one with a npn/pnp pair or nmos/pmos pair. They are reasonably simple.

4

he Wikipedia article had lots of extra stuff that doesn't apply to me: set/reset inputs, inverted outputs..

Yes it does apply to you.
Set is your faulty condition. Reset is when you want to put it back. Output is your control, inverted output you might need depending on the polarity of what you are trying to control.
I would suggest you need an RS flip flop.

5

BillO:
Not sure I understand your fear of software.

Because the faulty condition is power regulation. If you can't maintain Vsupply within tolerance, your software may or may not run properly. The transistors I chose will have a much, much higher tolerance for over-voltage, and will turn off (killing power) if severely under-volted. In the comparators, I've set a capacitor delay on the under-voltage, allowing load-dependent sags, and a carefully set instant-death on over-voltage. All of this seems easier and more reliable (to me) in the analog domain.

Grumpy_Mike:
Yes it does apply to you.

I think I didn't word that quite the way I intended it. I will use set, and Q (well, probably inverted Q actually, due to the polarity of the control) but I have no need of reset and the inverted output. Using 50% of the I/O is certainly possible, but I was beginning to wonder if it was still the right tool for the job then. There were also propagation delay issues, race conditions, and the (highly unlikely in my case) possibility of invalid input combinations that I'd have to deal with. I'm sure most of that stuff isn't fatal since I'm not dealing with high-speed digital logic, or conversely that the same problems wouldn't apply (possibly worse) in a discrete circuit. At my experience level, I just don't know. So I try to keep it as simple as possible.

dhenry:
Your A will work and B will not.

Now, what you are looking for is essentially a SCR. You can get a scr, or build one with a npn/pnp pair or nmos/pmos pair. They are reasonably simple.

Yep, I had a hunch. B seemed like a fluke of simplified ideal component simulation rather than a model of dependable real-world operation. Looking at it again, the difference between the two is minus one diode, plus two resistors and a P-FET. I think I can live with that.

I'll look into SCRs, that's a new one to me. After a cursory glance at the Wikipedia page, they seem to operate on current, so I'd need to manufacture a voltage-dependent load. I think for now I'll go with the working solution and revisit this later.

Thanks so much for the feedback guys. :slight_smile: