Thumb/Thumb2 are a subset of the full ARM instruction set, the instructions fit into 16 bits and therefore are more efficient WRT flash usage.
CMSIS is really (AFAIK) just a lot of defines and structs that tend to provide an abstraction layer, but it's only one level about dicking around with raw addresses. So my example
LPC_UART0->THR
is really just a human-friendly version of the address 0x40008000, while the Transmit Holding Reg of UART1
LPC_UART1->THR
is at 0x4000C000
Here is an example of the USART0 part of a header file that implements the CMSIS stuff
typedef struct { /*!< (@ 0x40008000) UART0 Structure */
union {
__IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */
__IO uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
__I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
};
union {
__IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0) */
__IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB = 1) */
};
union {
__IO uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls UART FIFO usage and modes. */
__I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< (@ 0x40008010) Modem control register */
__I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< (@ 0x40008018) Modem status register */
__IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
__I uint32_t RESERVED0[1];
__IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
__I uint32_t RESERVED1[1];
__IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */
__I uint32_t RESERVED2[6];
__IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
__I uint32_t FIFOLVL; /*!< (@ 0x40008058) FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
} LPC_UART0_Type;
The SAM will have similar but I'm having a hard time finding it in the 1.5 install.
Rob