Hi, since this problem doesn’t let me sleep, I tried simulating it and finally got LTSpice up and running. Unfortunately, the results puzzle me.
The first pulse is as expected: It sends a shorter pulse over the cap to RST. But what the hell is going on after the second pulse? Where do 6V come from? Is this a simulation artifact and how do I avoid it? I would expect that V(emitter) goes to 3.3V-transistor dropoff, and at the next LOW pulse gets
Everything I configured should be visible in the schematic. Since some curves overlap:
- V(p1) follows V(d0), except for the small, visible transient at the beginning of the first LOW pulse.
- V(d0) is as configures: starts 3.3V, drops to low after 1s, then does a cycle of 3s LOW, 2s HIGH.
- V(rst) is at 3.3V all the time, except for the visible LOW spike at 1s.