M4 and M7 acces to buffer in SRAM

Official Hardware Mega GIGA R1 WiFi
1

Hi,
I have project where I would like to use both cores M4 for data collecting with interrupts and M7 for data processing.
My question is how to transfer the data between M4 and M7 or does M7 see the SRAM used by M4?
The plan is M4 will create large buffer in SRAM and store the data there, then I would like to use M7 to access this buffer and get the data - is this possible?
If I will use RCP.call I am afraid it could be to slow.
Regards

2

Hi,

Yes, very much possible - I've been doing something similar for some time.

RPC is slow so I'm using a SRAM4 which is shared between cores.

I have a struct that defines my buffer and create a pointer to it in both cores, thus:

sharedLogData * const sharedLogDataPtr = (struct sharedLogData *)0x38000400;

You will need to disable caching of the D3 RAM on the M7, you can use this:

void log_mpu_config(void) {
  MPU_Region_InitTypeDef MPU_InitStruct;

  HAL_MPU_Disable();

  MPU_InitStruct.Enable           = MPU_REGION_ENABLE;
  MPU_InitStruct.BaseAddress      = D3_SRAM_BASE;
  MPU_InitStruct.Size             = MPU_REGION_SIZE_64KB;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable     = MPU_ACCESS_NOT_BUFFERABLE;
  MPU_InitStruct.IsCacheable      = MPU_ACCESS_NOT_CACHEABLE;
  MPU_InitStruct.IsShareable      = MPU_ACCESS_SHAREABLE;
  MPU_InitStruct.Number           = MPU_REGION_NUMBER15;
  MPU_InitStruct.TypeExtField     = MPU_TEX_LEVEL1;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec      = MPU_INSTRUCTION_ACCESS_ENABLE;
  
  HAL_MPU_ConfigRegion(&MPU_InitStruct);
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
3

Hi,
thank you very much for answer,
it looks a bit new for me, I have to test it.
Maybe if you can help me a bit more, my idea is:

  • define big array in sram finally probably whole 8MB, let say similar way as:
    myDataBuffer = (uint8_t *)mySDRAM.malloc(1000 * 1000 * sizeof(uint8_t));
  • M4 is saving data to it every interrupt occur.
  • M7 have access to it and can read the content of whole array.
  • probably I have to add kind of flag to avoid colision
    Regards
4

Hi,

I've corrected a typo in my first post, it's SRAM4 in domain 3 that I'm using. If you check out RM0399 ref manual section 2 for this mcu you can see the memory map.

SRAM4 is 64KB. If you need megabytes then SDRAM (which is on a separate chip and so slower) will be needed. I've not done this but this post is relevant Access of SDRAM by both M4 and M7 cores