M4 Express SAMD51 - Using TCC1 timer on multiple pins

[snoozerman]

Hello,
I am trying to set up PWM output on a AdaFruit Feather SAMD51 M4 Express board. I use the TCC1 timer peripheral for port PA19 and PA20 on normal PWM mode. PA19 uses TCC1/WO[3] and PA20 TCC1/WO[4] according to Table 6.1 in the SAMD51 manual.

It works fine for the PA19 (pin D9) but PA20 (pin D10) is just kept low. I cannot figure out why.

// Set-up timer TCC1 in Normal PWM mode for PA19 and PA20.
const uint16_t PERIOD = 0x3FFF; // 14 bits resolution

void setup() {
  // Set up the generic clock (GCLK6) used to clock timers
  GCLK->GENCTRL[6].reg = GCLK_GENCTRL_DIV(1) |       // Divide the 120MHz clock source by 1.
                         GCLK_GENCTRL_IDC |          // Set the duty cycle to 50/50 HIGH/LOW
                         GCLK_GENCTRL_GENEN |        // Enable GCLK6
                         GCLK_GENCTRL_SRC_DPLL0;     // Generate from 120MHz DPLL clock source
  while (GCLK->SYNCBUSY.bit.GENCTRL6);               // Wait for synchronization 

  GCLK->PCHCTRL[TCC1_GCLK_ID].reg = 
                        GCLK_PCHCTRL_CHEN |        // Enable perhipheral channel
                        GCLK_PCHCTRL_GEN_GCLK6;    // Connect generic clock 6 to TCC1, PCHCTRL[25]

  // Enable the peripheral multiplexer on PA19
  PORT->Group[0].PINCFG[19].bit.PMUXEN = 1;
  PORT->Group[0].PINCFG[20].bit.PMUXEN = 1;
 
  // Set PA19, PA20 the peripheral multiplexer to peripheral F(5): TCC1, Channel 3 and 4.
  PORT->Group[0].PMUX[9].reg  |= PORT_PMUX_PMUXO(5);
  PORT->Group[0].PMUX[10].reg |= PORT_PMUX_PMUXE(5);
 
  TCC1->CTRLA.reg = TCC_CTRLA_PRESCALER_DIV1 |    // Set prescaler to 1
                    TCC_CTRLA_PRESCSYNC_PRESC;    // Set the reset/reload to trigger on prescaler clock
  TCC1->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM;         // Set-up timer for Normal PWM mode (NPWM)
  TCC1->PER.reg = PERIOD;                         // Set period
  TCC1->CC[3].reg = 9999;                         // Set the duty cycle
  TCC1->CC[4].reg = 9999;                         // Set the duty cycle

  TCC1->CTRLA.bit.ENABLE = 1;                     // Enable timer TCC1
  while (TCC1->SYNCBUSY.bit.ENABLE);              // Wait for synchronization
}

void loop() {
  // Update duty-cycles
  
  // PA19 (D9) - works
  TCC1->CC[3].reg = (TCC1->CC[3].reg + 4) % (PERIOD+1);
  // PA20 (D10) - does not work
  TCC1->CC[4].reg = (TCC1->CC[4].reg + 4) % (PERIOD+1);
  delay(1);
}

All advices appreciated!

[snoozerman]

After trial and error, I now got PWM also on PA20 (pin 10). I needed to counter compare register 0 instead of 4. But I do not understand why..

These changes were need;

// Was  TCC1->CC[4].reg = 9999;
TCC1->CC[0].reg = 9999; 

// Was TCC1->CC[4].reg = (TCC1->CC[4].reg + 4) % (PERIOD+1);
TCC1->CC[0].reg = (TCC1->CC[0].reg + 4) % (PERIOD+1); 

SAMD manual Table 6-1. "Multiplexed Peripheral Signals" states for PA20 that TCC1/WO[4] is used for peripheral F(5). So I though the count compare register would need to be CC[4] as well. But obviously not. How can I know what CC-register to use for the single slope PWM mode then?

[westfw]

Are not some of the WOx outputs actually alternate polarities of lower CC register match decision? Eg tcc1 has 8 outputs but only 4 CC registers, and WO4 is a shadow of CC0…

[snoozerman]

The TCC wave registry does have bits to set polarity on WO 0 to 5 (as I interpret it). I guess each of these POL 0 to 5 corresponds to a WO 0 to 5.

You may be right that WO[4] somehow shadows CC[0]. But where is that stated in the manual I wonder? Can't find it mentioned anywhere. Or, more likely, I don't realize it is mentioned somewhere...

B.t.w. below is from Table 6.1 Multiplexed Peripheral Signals. This is what bugs me. TCC1 for PA20 should use WO[4]. So the I expected CC[4] to be used.

[westfw]

It's not quite like I thought it was, but TCC1 only has 4 CC registers, so there is no CC[4]

I think I may have gotten the "shadowing" idea from a different chip, "assuming" that "TCCs" would be identical (but apparently they're not even the same as each other within the same chip. Sigh.) But see section 49.6.3.8 on the "waveform extension."