One aspect, I think, is just raw edge transition speed. Even if you are only toggling a I/O pin at 1 mhz it's edge rise and fall times are determined by the fundamental internal chip clock speed, so likely to cause more problems when using a 80hmz chip then a 16mhz chip, no?
I can understand that as a reasonable position, but how do I derive an answer?
I can't find the spec for rise/fall-time for an ATmega, or the LPC1343, so let me try the STM32F103RB, as on a Maple.
I can find the rise/fall-time for the STM32F103.
I also see (in Table 19 of ST's document 13902) that the I/O pins can be configured for 50MHz, 10MHz, or 2MHz output. I've not found a good description of this yet, but I assume it is a bandwidth limiting mechanism (like some RS485 drivers).
Okay, so let's start by running the Cortex-M3 at 16MHz, using an 8MHz crystal. So it looks no worse than an ATmega328 with a 16MHz crystal.
Further, let's assume that the 10MHz does mean the rise time is bandwidth limited (and I'd be willing to go down to 2MHz if it makes the answer unambiguous).
Also, let's assume that the decoupling follows ST's design guidelines (which are intended for 72MHz operation).
- Would it be likely that a stable double-sided PCB could be made for a 16MHz STM32F103RB with an 8MHz crystal?
2, What frequency might the internal speed of the Microcontroller go up to, on a well designed, but simple technology, double sided PCB, and remain stable?
Anyone able to offer some guidance what might be feasible, and what would help improve it (other than these articles http://www.ultracad.com/article_outline.htm)?
GB-?