OK, so it looks like this:
MCP4922 PIN CONNECTED
PIN FUNCTION TO
------- -------- ---
1 VDD 5V
2 NC ---
3 CS DUE PIN 10 (CS)
4 SCK DUE ICSP-3 (SCK)
5 SDI DUE ICSP-4 (MOSI)
6 NC ---
7 NC ---
8 LDAC GND
9 SHDN 5V
10 VOUTB -> DAC B OUT
11 VREFB 2.5V - RESISTIVE DIVIDER
12 VSS GND
13 VREFA 2.5V - RESISTIVE DIVIDER
14 VOUTA -> DAC A OUT
Changes I've made to your list:
- Added the Due pin number for CS that corresponds to your code, pin 10.
- Added the Due ICSP designations for those pins.
- Added a connection between MCP4922 9, SHDN, the shutdown pin, and 5V. If that pin is left open and read by the MCP4922 as a low input, the DAC shuts down. If you don't use that pin, it should be tied high.
It's worth noting that you can use the same resistive divider to supply VREFA and VREFB. You may well have done it that way; I mention it for completeness.
Here's something else to note: The MCP4922's datasheet shows VIH, the minimum voltage that the circuit promises to read as high, as 0.7VDD. That's 3.5V. The Due's logic outputs can only be as high as 3.3V, and that's less than VIH. There's a possibility that the MCP4922 will not be able to see a high input from the Due, and will thus give unexpected results. It's not particularly likely, as 3.3V is pretty close to VIH, but it's not impossible for the MCP4922 to read lows where it should see highs under some conditions, and for some unlucky MCP5922's to never read a high in this circuit. If you start getting unexpected results, that's a possible reason. A remedy would be to apply some level-shifting between the Due and the MCP4922
With LDAC grounded, the input registers transfer immediately to the DAC output when they're received. It's easy, but the DAC is less functional in that mode. The purpose of LDAC is to allow synchronization of the A and B outputs, and other DAC's as well, if the device has others. You can load register A, load register B, then pulse LDAC, and both outputs will update simultaneously. You can also use LDAC for hardware-controlled timing, by loading the A and B registers, and letting a hardware timer output control the LDAC input. The outputs update precisely on the clock, and you can load the next values into the registers in response to the timer, by polling or interrupt.
Note that the function of the LDAC pin is controlled by bit 14 of the input message: if that's a 1, LDAC is active; if it's a 0, LDAC has no effect, and the DAC register transfers to the output immediately. Your code sets bit 14, so LDAC is active.