I think you may be missing the detail that I'm placing the timer in CTC mode (specifically, mode 4). Here's a nice quote from page 142 of the datasheet (in the Output Compare Units section):
If I can define the period, I can define the frequency... Think of it this way: I'm counting to some value, "OCR", then the timer value resets to zero and continues counting. Each time the counter matches "OCR", the pin is toggled:
(assume step pin starts LOW, timer count is initially set to zero, and OCR set to some value greater than zero)
2) timer count reaches OCR:
- step pin set HIGH (toggled from LOW)
- timer count reset to zero
- timer count reaches OCR:
- step pin set LOW (toggled from HIGH)
- timer count reset to zero
- timer count reaches OCR:
- step pin set HIGH (toggled from LOW)
- timer count reset to zero
As you can see, the OCR value represents the "half period" of the period between step pulses from the output compare unit. If I vary this OCR value at some points throughout the timer operation (using the ISR on the output compare match in my CL42T test code), then I vary the frequency of the output on the OCnx pin... Again, please see my "simple example" above which demonstrates this ability.