This is my first (and very long) post in this forum. I may have included way too much detail and background to explain my inquiries, so if you don't want the background, skip to the start of the **** section (I did so because I am hoping someone might happen to have a better solution than the one I am looking for). If you know of a better forum to post this, suggestions are very welcome.
I have made a seemingly foolish mistake and may have loaded my SPI bus with far too much capacitance. I have a PCB with a mega clone that I have designed to control devices on 4 other PCBs over SPI. Each of these four other boards are connected to the mega clone board via ~6" of ribbon cable and each has 20 SPI devices (4 MCP23S17 and 16 DAC8554) When I attach a single board to the mega clone board, SPI comm works fine, but when I attach more than 1 of the device boards to the mega clone board, the MCP23S17's program, but the DAC8554's do not.
My intuition is that this is due to the extra capacitance on the SCK and MOSI lines from the additional board. I measured it and both the SCK and MOSI lines have ~120pF of capacitance each ( :o ). In this Microchip forum post about max number of SPI Slaves, user tunelabguy suggests to keep the capacitive load under 50pF. I am not sure where this suggestion comes from without knowing what device is the master, but my Atmega 2560 seems to do fine with the ~120pF load of one device board. I am curious how to determine the max capacitive load (SPI pins drive strength?) of the Atmega 2560 SPI pins. I figured the SCK and MOSI signals could be slewing so much that it would be ambiguous as the what the data level was at the clock transition, but after putting these lines under the scope (and adding an additional 16pF of capacitance due to the probe) the SCK and MOSI signals are very clearly defined. A screen capture is shown below.
My next concern was rise and fall time of the signals. With one board attached the rise times for both SCK and MOSI were 25ns, with two device boards ~35ns and with three ~40ns. The data sheet for the the MCP23S17 declares a maximum rise time of 2us, and the data sheet for the DAC8554 says "all input signals are specified with t_R = t_F = 3ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL + V_IH)/2." With my 5V rail I take this to mean 3ns to transition from 2.5V to either 4.5V or 0.5V, but I'm not sure if this is their testing case, typical use case, or maximum. This would explain why the MCP23S17 works but the DAC8554 does not. However, the 25ns rise time of the single working device board case breaks down to ~10ns during 2.5V to 4.5V transition, which is considerably larger than 3ns. The strangest part of all... if i put 22pF of capacitance across MOSI and GND, any number of boards works... I have probes on both MOSI and SCK and they are identical, with or without this magical 22pF cap.
I do not know what is causing this, but this "magic cap" seems to me like a hack of a fix. I feel like i am looking in the wrong place, so I would like to meet the DAC8554's data sheets rise time suggestion if possible.
So here is why I have come to the forum. I found a post where someone was able to speed up the rise time of their pins on a teensy. I am wondering if the SPI pins on my mega clone can be similarly changed to have a faster rise time, or if they are already set in the fastest setting. If so where do I need to alter the arduino code? I am working in Atmel Studio with Visual micro, so essentially Arduino with a more traditional development environment. I would also like to know how to determine the capacitive load capabilities of the SPI pins so I can better plan my next project or my fix to this one.