MKRVIDOR embedded SDRAM signals

Hi

I'm working with an MKR Vidor board, and trying to save data on the embedded SDRAM memory, got the example template and look at the input and outputs form the board, but I don't really understand some of the signals.

// SDRAM
output oSDRAM_CLK,
output [11:0] oSDRAM_ADDR,
output [1:0] oSDRAM_BA,
output oSDRAM_CASn,
output oSDRAM_CKE,
output oSDRAM_CSn,
inout [15:0] bSDRAM_DQ,
output [1:0] oSDRAM_DQM,
output oSDRAM_RASn,
output oSDRAM_WEn,

Is there somewhere to find the full name of all these signals, and some examples about how to use it?

I've checked the pinout, and some of the schematics available on the tech specs, but I don't really get the use of them.

My Best regards

Hi,

You need some kind of SDRAM controller. Fpga4fun site has some good explanation how it work and easy example.

fpga4fun.com

SDRAM info
simple SDRAM controller

Edit:
You can also find some simple controllers with google or from opencores.org. Note sure was Altera/Intel SDRAM controller free which would give you access to platform designer tool and it have avalon interface. You can also use platform designer to contvert it to AXI4 (Lite)

Thanks for the information Limba

Bit I'm still looking for the name and function of the signals that I found on the MKRVIDOR4000_top.v file, in order to use it to code or test a SDRAM driver, I've been looking on intel files like:

But I couldn't find anything about those signals (or any SDRAM signals at all)

BR

Edit: Also, I would like to know if I need to use all of those signals in order to make use of the embedded SDRAM

The SDRAM signals are related to the AS4C4M16SA-7BCN chip. So you can't find them in the Cyclone10 datasheets. You must read the datasheet of the SDRAM chip.

The SDRAM behaves like a finite state machine, so the meaning of the pins changes with the variation of the internal state and the state of the other pins.

This table, present in the datasheet, shows the meaning of the various pins. You must read the details of the individual commands to understand how to use them:

The controller for the SDRAM, which will be implemented in the FPGA, will also be a finite state machine synchronized with the one inside the chip.

These signals are in page 2 in schematics.
https://content.arduino.cc/assets/vidor_c10_sch.zip

Edit:
Buttom of "simple SDRAM controller" has link to code "The complete demo code is available here." where "here" word contains link zip file that contains SDRAM_ctrl.v.

The SDRAM controller used by the official repos, altera_avalon_new_sdram_controller, is not available to Quartus Lite users.

I have created an open source controller for AS4C4M16SA: GitHub - hdl-util/sdram-controller: Generic FPGA SDRAM controller, originally made for AS4C4M16SA. Not sure how compatible it is with the Arduino code but it is worth a try.

I'm planning on write my own SDRAM controller, to use an external ADC to sample a signal and store the samples on the SDRAM.

The Chip datasheet that @riccardo_giacomazzi post was really helpful to me, thanks a lot.

pusirame, would you tell me how to test your'e controller?

Here's a demo of it working.

The files you need to run it are:

You can add them to a new quartus project and things should compile fine. If you run into issues let me know. Alternatively, you can install and use hdlmake for easier setup of the project as follows:

git clone https://github.com/hdl-util/sdram_controller
cd sdram_controller/syn/mkrvidor4000_quartus
# Get dependencies from GitHub automatically
hdlmake fetch
# Creates a Makefile
hdlmake
# Create Quartus project using Makefile
make project
# Open Quartus Project
quartus as4c4m16sa-demo.qpf
# now compile and blast the sof file to the Vidor 4000

The screen will look like this in case of success:

Which means the entire DRAM was written with a 16-bit counter equal to the 16 LSBs of each address, and then the value read from each address was correct.

purisame:
The SDRAM controller used by the official repos, altera_avalon_new_sdram_controller, is not available to Quartus Lite users.

What do you mean "not available"?
The _lite version of project builds just fine, and the only difference is using Nios /e instead of /f, and missing 16550_uart, both requiring license.
But I din't hear about sdram controller requiring license, nor do I have it.

VStrakh:
What do you mean "not available"?

It wasn't in the IP catalog for Quartus Lite and I couldn't find much about it online other than that it is part of Intel's Avalon interface. I can't find much for Avalon in the IP catalog either other than simulation stuff, JTAG, and SPI.

VStrakh:
The _lite version of project builds just fine, and the only difference is using Nios /e instead of /f, and missing 16550_uart, both requiring license.
But I din't hear about sdram controller requiring license, nor do I have it.

This post from 2017 on the Intel forum suggested that it would not be available to Quartus lite users, which is why I thought it must not be available anymore.

So maybe it still works because it's needed for NIOS, though it's not listed in the catalog?

Yeah, I've seen that post too.

But the controller is here, available for free in Quartus Prime Lite 18.1, as required by VidorBitstream repository's readme.
It's not in the list of IP Catalog that opens from the quartus main window, it's in the IP catalog of qsys editor/platform designer, under "SDRAM -> SDRAM Controller Intel FPGA IP"

A pic with quartus edition and version listed, plus the ip catalogs to confirm the controller is available.

Ok, thank you for clarifying this VStrakh.

Just installed Quartus Prime Lite 19.1, I didn't do it earlier, also being scared off by that message about sdram controller "dropped in the future".

It looks like sdram controller is still available for free.