When I attempt to acquire inputs from two cascaded NXP 74HC597 shift registers, all I get is nulls. I wrote a routine to generate effectively the same purpose that I can adjust the periods. With a slowed clock rate the 597's work correctly. While monitoring the chain's SData line I see the data shifting out. So my question is where in the core source code is the shiftin() function so I can make a modified copy which can be down clocked.
The file is "wiring_shift.c", and in my installation, it's located in "\Arduino\hardware\arduino\avr\cores\arduino".
This is the function:-
uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
{
uint8_t value = 0;
uint8_t i;
for (i = 0; i < 8; ++i)
{
digitalWrite(clockPin, HIGH);
if (bitOrder == LSBFIRST)
value |= digitalRead(dataPin) << i;
else
value |= digitalRead(dataPin) << (7 - i);
digitalWrite(clockPin, LOW);
}
return value;
}
According to the times in Table 7 of the datasheet,
http://www.nxp.com/documents/data_sheet/74HC_HCT597.pdf
I would expect that part to be able to run at SPI clock speed of 8 MHz, no slowdown should be needed.
How do you have it wired up? Do you have 0.1uF/100nF caps on the Vcc pin to Gnd?
Code should be something like this, with MR/ connected to +5 and DS to GND.
digitalWrite(STCP, HIGH); // capture data at input pins
digitalWrite (STCP, LOW);
digitalWrite (PL, LOW); // move data into the output shift register
digitalWrite ((PL, HIGH);
inbyte1 = SPI.transfer(0); // clock the data into Arduino. SCK/13 to SHCP, MISO/12 to Q
inbyte2 = SPI.transfer(0); // clock the data into Arduino.
Each card has no less than 4 each 1uF ceramic caps distributed along the power busses. The cards are RS# 276-168B one card is fashioned into a 5 slot backplane with 30 pin headers, into this are 3 cards, one housing the Arduino Micro, one containing the 2 597's and the third having 3 CD4069's serving as signal conditioners for an array of RC pulse delays. The delay card serves the 597's with data inputs and a reference STCK such that a parasitic capacitance change from a touch pad causes the rising edge of the channel's strobe to arrive after STCK (key presence, logical 0) or before STCK (key no presence, logical 1). My initial design used a LS374 for capture, then would have been used to load a 597, but I realised the storage register could facilitate the same function as the preceding LS374 without requiring 2 additional chips and the real-estate associated therewith. I am not using the SPI built in hardware, it will be required later for the 32 channels of source drivers. I would also like to thank-you for the response.
SPI is a parallel bus, all devices get SCK-MISO-MOSI connected in parallel, with a unique chip select for each device ('device' can be a group of daisychained shift registers). Each device needs to have a tristate output controlled by it's chip select so as not to drive MISO when not selected, this can be 1 gate of a 74HC125 for example.
You really need 0.1uF cap at each device's VCC pin in addition to the 1uF cap on the power bus.
Your explanation does not provide insight as to when data is captured and when it is read out.
The 74LS374's in the schematic are being emulated by the storage register in the 74LS597's.
The issue was the fashion I was trying to use shiftIn(). I was not treating it as a function, but was trying to pass a buffer to it in the call arguments.
ajofscott:
The issue was the fashion I was trying to use shiftIn(). I was not treating it as a function, but was trying to pass a buffer to it in the call arguments.
I'm surprised the compiler let you do that without complaining. Perhaps you should turn up your warning levels in Preferences. Better too many warnings than too few!