the P-channel mosfet in my circuit is turning on for a short time and i’d like to know why.
The circuit principle is rather simple. I’m supplying 5V at the left (TP_SUP) and would like the MOSFET to block the current until the botton is pressed so the DCDC will activate and the uC will start and pull the latch pin up. Unfortunately i can see that the DCDC is already getting activated as soon as i connect the 5V, but only for a short time.
There are parasitic capacitors between gate-source C_gs and gate-drain C_gd, they form an AC voltage divider with respect to the drain voltage (your DC/DC VIN). For DMP1045U the divider ratio is 1:5 (calculated from datasheet values). Upon fast rise of the input voltage the gate voltage transiently takes values different from the USB voltage input due to the AC voltage divider. The voltage difference becomes up to V_gs = -0.9V in your case (see simulation below). This is enough to switch on the MOSFET for a short time (typ Vgs_threshold = -0.55V).
This problem only exists at high enough slew rate, where the impedance Z=1/omega * C_gs becomes much smaller than R13. At slower rise rates the R13 dominates the behavior of the voltage divider and all is good.
You can calculate C_gs and C_gd from datasheet values like this:
C_gd = Crss = 235pF
C_gs = Ciss - Crss = 1100pF
Your solutions options
A: Increase C_gs/C_gd ratio to >15:
Manually increase C_gs by adding a 10nF capacitor parallel to R13 (easiest to do)
Choose other MOSFET model respecting that condition without additional components
B: Reduce R13 (may not be sufficient depending on the slew rate during mechanical hot-plug of 5V)
C: Reduce the slew rate on voltage input. Slew rate of USB-C is specified as max 160mV/us (as far as ChatGPT knows) thus 30us from 0V to 5V. You need at least ~500us slew rate for your case to work.
Have you tried grounding the base of Q4 while powering up? If that keeps it off, then it is unlikely to be self turn on, and more likely to be the latch pin going high during boot.
I agree with @fabelizer and you need to consider the leakage current through the diodes
Self turn is a rare occurance. I've done many SMPS designs and never had it happen.
I think the simulation draws a pretty clear picture.
If diode leakage was causing the LATCH_PIN to activate, it would permanently activate the MOSFET and not only for a short time after plugging. But I agree, its an easy test to pull the gate hard to GND and try again.
I've observed self turn-on in a few designs over the years. It often goes unnoticed if you don't explicitly look for it as it's often without observable symptoms. And it happens easily. Just put a cap on the wrong side of the MOSFET and you're there. Also many (older) MOSFET models have poor C_gs/C_gd ratio (like this one). In combination with very low V_gs_threshold it happens even without external caps.
The way I think of it is that with no power you start out with all the mosfet pins discharged and at ground. Then suddenly the rail goes to 5V, low impedance. The source pin immediately also goes to 5V, but the gate is still at ground, so the mosfet turns on. Then as the gate charges up through the resistor, it soon gets to the threshold voltage, and the mosfet shuts off.
The capacitor will pass the sudden increase in rail voltage through to the gate, because rapidly changing voltages pass through capacitors. The gate comes up at almost the same time as the source, and the mosfet stays off. So it's just a question of picking the right capacitor value that prevents the turn-on.
I've been told that this explanation is wrong. But adding the capacitor does work, so maybe that's still the solution for (in my case) the wrong reason.
I don’t have an 10nF cap here (yet) to test it, but here’s an update:
Pulling Q4 Base hard to GND didn’t change anything
I reduced R13 from 100k to 47k, didn’t change anything
But i noticed something else: The 3.4V network is constantly slightly on, at around 1.6V, even though the DCDC should not get any power. I made a short video which describes it a little better:
