MP3 Player Breakout with I2S Interface

Hi All.

Wondering if anyone has a recommendation for an MP3 Player breakout module. The catch is, I want an I2S Audio output. The application is to stream bytes of an MP3 file bytes in over SPI from a processor (say a Teensy 3.2) and output the audio via I2S.

The VS1053 Breakout from Adafruit is ALMOST ideal for this. But, the VS1053’s I2S interface only supports the 32-bit I2S frame format (i.e. BCLK = 32 x Fs). But, my application needs 64-bit I2S format (BCLK = 64 x Fs). So, something similar to the Adafruit board but with a better CODEC.

Note, I’m not talking about actual number of Audio bits per sample (16 per channel is fine), but the containing I2S frame itself. If you know about I2S, you’ll understand what I mean.

Thanks.

Hi! I have had something similar where the application required 64xFS for the PLL to lock to, while 16b format was in principle fine. I solved it by using a clock doubler. Might work for you as well, depending a bit on the exact nature of the problem.

Thanks for the reply, but I don’t see how this alone will help. While the BCLK frequency will be correct, you’ll double sample every data bit. So, the bit stream will now be 32-bits (per L / R channel) long and consist of repeated bits:

L00, L00, L01, L01, L02, ... L15, L15, R00, R00, R01, R01, R02, R02, ... R15, R15

Thanks, good information

Hi gvalvo,

I see what you mean. In my case I can set my i2s receiver (audio amp) to process 16b audio with the 32xFS bit clock. However, I need a 64xFS as master clock input for the PLL to lock to for internal DAC clock. So bit this master clock is derived from the bit clock by doubling.

oortgiesenrien: Hi gvalvo,

I see what you mean. In my case I can set my i2s receiver (audio amp) to process 16b audio with the 32xFS bit clock. However, I need a 64xFS as master clock input for the PLL to lock to for internal DAC clock. So bit this master clock is derived from the bit clock by doubling.

@oortgiesenrien, OK, got it. Thinking about it a little more, I could make it work. After doubling the clock (to BCLK = 64xFs), I'd be running the (double-sampled) I2S data into a processor's I2S interface. My code could then decimate the sampled data to recover the original 16-bit (per channel) stream and zero-pad the last 16 bits of each channel. That would give me the original 16 bits / channel data but justified into a 32 bit / channel I2S stream.

The phase of the doubled clock with respect to the data and LRCLK would have to be correct. I'll look into a SiLabs PLL for that. What did you use?

Thanks for the idea.

I’m using MKRZERO in combination with an amplifier - Infineon MA12070P to drive hifi speakers. It has a build in PLL and DAC that accepts the previously described combination of master clock, bit clock, word clock, and data. I can share a block diagram and code later.

I am using the below clock multiplier as doubler. It is PLL based so phase locked.

https://www.onsemi.com/pub/Collateral/NB3N511-D.PDF

What is your application exactly if I may ask?

Thanks for the PLL reference.

The application is to drive the I2S output data from the MP3 player into the I2S Input of a Teensy 3.x Board and the process it using the Teensy Audio Library. Then, output to a I2S amplifier.

Every device in the above chain (except the MP3 player that I linked) uses 16-bit /channel audio data embedded in a BCLK = 64xFs I2S frame.