Below is a 8 bit R2R DAC circuit that I built for use with my Parallax chips. Its intent is to be cascaded with the analog out of one feeding the analog reference (AIN) of the second DAC. By feeding the DAC's with a bitpattern incrementing to a peak the decrementing to a min and incrementing back up the DAC will produce a symmetrical ramp. This ramp when provided to the second stage will linearly modify the conversion ratio of the second DAC such that if its bitpattern matches the period and waveshape of the first and is time shifted 90 degrees to the first, as symmetrical sinewave is the result. Mathmatically the derivative of a sine is a symmetrical ramp, if a further derivative is applied , a Square wave of 50% duty cycle is the result. In out beloved Mega chips there is a similar circuit whose analog output is compared to the selected analog pin, the bits driving the DAC come from a ripple carry counter. When the comparison of the 2 signals changes from low meaning the analog pin's voltage is greater than or equal to the DAC, the ADC signals "Conversion complete" and the current count of the Ripple counter is latched and made ready for retrieval by the Mega's databuss.
I can provide you with the board layout on a request basis. The board was created in WinBoard 2.4 and I doubt may of you have the WinDraft/WinBoard suite.