Is there a reason to not want to connect SCK, MISO, MOSI to all devices and just give each its own Slave Select?
The chip still just has 1 8-bit bus internally, and only runs 1 instruction at a time.
If you were reading one file and writing another ‘at the same time’ then having them on different cards on different SPI buses would save time since both would stay open, selected and positioned all the time. On one bus, you read then close the file, deselect the SD, select the other SD, initialize, open file, seek, write, close, deselect, etc. You do a lot again and again just getting to where the card on the dedicated bus only has to do once.
If you only append-write one file to a card, it will not get shotgunned.
Instead of sorting, write ordered-link files or better yet have a PC do that and use the links in the sketch.
But when I saw the 2560 having 4 UARTs capable of MSPIM in the datasheet, I thought network. I think that Grumpy Mike (or AWOL?) remembers the Transputer and the Occam language. IIRC in 1985 the nodes were 8 MHz Von Neumann computers with 4 high speed serial links each. Only thing is that AVR’s are not Von Neumann, but Harvard architecture? However hard it’s proving, there is some effort to bring Occam to AVR (328’s). Occam would be a good path for interconnected 2560’s? They could have 64k RAM using external RAM. They’d have an SPI bus channel each, for SD of course. But what to do with it? Blink leds?
Back in the later 80’s I read of a Cal Tech machine made of 64 PC/XT mobos serial linked as a 6-dimension hypercube, 2^6=64. It had 1/10th the power of a CRAY but could do physics problems that formerly only CRAY-class computers could do.
I wonder how many 2560’s it would take to match my SEMPRON 2600 and mobo?