Nand gate array

Is there anyway to turn the arduino into an nand gate array? (18 gates)

Thank you ;)

Yes, but the propagation delay will be much worse than if you were to use five 7400s instead. More expensive too.

Good point. But It would be more than just a nand gate array. One such that it would depend on a 12 digit key to turn specific gates on and off.

Also, it would have to be at least a Mega, otherwise you wouldn't have enough I/O pins. Those 7400s are looking better value all the time ;)

Lol I'd say so. But where i get stumped is how do I make the gates in the 7400's switch on and off based on a software key?

I'm not sure I understan what you mean by a "software key"?

Are the "12 digits" binary? Decimal?

If you're meaning to have the ability to simulate 18 NAND gates externally, you'll need at least 54 pins, assuming dual input NANDs.

If, however, you want 18 NAND objects, then you just need a few K of code space, plus a few extra bytes of RAM to represent the I/O states.

Your question is still a bit unclear. Are you processing 18 dual input NANDs or are you just wanting to perform some form of output based on some form of input. Is there time restraints, ie action on immediate input change or can you allow scanning of inputs. If scanning is allowed, then a matrix input would reduce the number of input pins?

Ok, before anyone thinks I'm up to something mischievous I need to lay out the bottom line. I am in no way trying to intercept any kind of protected information, I'm merely trying to understand what this system does and maybe apply towards other means.

But this link is for a patent that includes a gate array. It should fill in the blanks. But what I'm trying to figure out is how a 24 digit key affects the gate array in this particular patent. I'm still not understanding how the two come together. Maybe someone with a little more patience and a lot more engineering knowledge can help me.

Here it is...

http://www.google.com/patents?id=kbs4AAAAEBAJ&printsec=abstract&zoom=4&source=gbs_overview_r&cad=0

Thanks guys! :)

OK. The patent is using XOR and NOR gates which is what is commonly used for encoding systems. It's been a while since I have had to play with this logic so here is a quick explanation of a very simple system.

Any kind of data can be encoded against a key, the key being some data length, either 8 or 16 bits. The data to be encoded has the key applied to it. A XOR logic is: 0+0 = 0 0+1=1 1+0=1 1+1=0

So a key of 10011001 in binary applied to random data would produce a output like:

10111101 = 00100100 01110011 = 11101010

Getting the data back, you need the key above and apply the same logic so:

00100100 with XOR key 10011001 = 10111101

Basic lesson over, you can now alter the above in many way to make the output stream more differcult to decode (crack) by rotating the key on every data encode, or use a 16 or 32 bit key. Maybe use a sequence of XOR then XNOR, NAND then AND. Another method could be to use the encoded output byte as the input to the next byte to be encoded.

By the way, a 18 input NAND gate is the same as a 18 bit key. If you need that level of encoding, use 24 bit which would be 3 bytes for the key.

Hope this helps. Have fun.....

Ok, in the code memory, would it just continuously repeat the "key" in binary as the secondary input to the gates?

Hold keys in code space or where ever you want to put them. There are many different ways to implement this type of encoding. Repeat or sequence keys. If you are using discrete logic, Apply data to one pin, the key to the second input or use code.

Get byte XOR with key = result