Yes you can read SPIx_POPR as a 32 bit register but only 16 bits are data. See 3.9.2.5
Figure 43-1. DSPI Block Diagram - shows 32bit data path to the shift register (and and extra for command)
Figure 43-1 is wrong. See rule 8 in my previous post. See 43.3.7 for the format of PUSHR.
43.1.2 "SPI frames longer than 16 bits can be supported using the continuous selection format"..
Continuous selection format just insures that CS remains low, it has nothing to do with the FIFOs.
CONT
Continuous Peripheral Chip Select Enable
Selects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selected
PCS signals to remain asserted between transfers.
0 Return PCSn signals to their inactive state between transfers.
1 Keep PCSn signals asserted between transfers.
43.4.2 "The SPI frames can be 32 bits long."..
Frames can be any size but a max of 16 bits can be transferred to/from the FIFOs. Unfortunately the data sheet uses Frame size for two things.
In the CTAR 43.3.3 it is how many bits wide the data field is in a FIFO.
In other places it is how many bits are sent in a transfer while CS is low.
Again the datasheet is a clue for Kinetis and point 8 above applies to many sections.