The VPORT register is located in the I/O register area and supports IN/OUT and SBI/CBI instructions, so access is fast (single cycle).
Since the PORT register is accessed using the LD/ST instruction, ST instruction is delayed by one cycle than OUT instruction.
(Reading is also one cycle delayed than IN instruction if optimized to LDS instruction.)
But PORT register has SET, CLR and TGL registers.
This makes it faster if for use by RMW(read modify write) with more than 2 bits.
(If 1 bit RMW, faster SBI/CBI instructions.)
However, since it is a difference of 1 clock or 2 clocks, if you don't need to ultimately optimize with the assembler level (a.k.a. if annoy even 1 cpu clock), you do not need to worry about chosen.