What do I get of this? What happens if one of the two participants puts the OUT pin to HIGH, and what happens if both have it set to HIGH or LOW?
How I see it: If neither of them has the OUT pin set to high, it's an open circuit and no voltage is received by the IN pins.
If one of them (lets call it sender) sets the OUT pin to HIGH, the senders IN pin will be HIGH, no? Shouldn't the second participant have voltage on it's IN pin in this case?
If both transistors are off, their resistance is very high, much more than the PULLUP resistor.
Therefore all the +V voltage will drop across the collectors to GND.
With all the voltage across the collectors to ground the inputs will see +V, or a high.
The GND is the negative terminal of the power supply.
The whole point is that the two outputs can differ (ie one HIGH one LOW) without large
(destructive) currents flowing. It is up to the connected nodes to arbitrate their usage of
the bus meaningfully, but the arrangement allows any node to transmit without risk of damage.
The arrangement also can reduce the risk of back-powering a circuit through its data
lines as the pull up resistor limits the maximum current, should one of the nodes be
unpowered.
Point being if each uP has one input and one wired OR /AND gate output, any uP can assert
a LOW on the bus triggering some S/W protocol to determined which uP pushed the PANIC button. Can't say I have ever seen this scheme before but it definitely can be
made to work if done properly.
Yes, it does and your memory is fine, but the difference is I2C has a protocol and the S/W is available and allows for much more complex communication. (although there is no choice available for the I/O pins. They must be A4 & A5 (AFAIK).