I worked with the overclocking routine from Graham (the one from ard_newbie has 2 EFC statements less) and saw that overclocking speedup was really not happening for 192MHz. Next I created sample sketch that does not rely on anything and creates the delay by a for loop with volatile variable executing 3,500,000 times. The piece of assembler code generated for that for loop takes 12 clock cycles, so both for loops together take 1 second with standard Due @84MHz. Also I did not rely on anything from Due for time measuring but used my small oscilloscope (to measure the time taken for 3 HIGH/LOW transitions).
This is oscilloscope display showing 2450ms for 102MHz Due CPU clock:
This is the table where I measured 3rd column with below sketch for MULA values from column 1:
This is the chart that compares measured times with ideal values (3000/(MULA+1)*14):
This is the sketch:
void setup() {
#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(16UL) | CKGR_PLLAR_PLLACOUNT(0x3fUL) | CKGR_PLLAR_DIVA(1UL))
#define SYS_BOARD_MCKR ( PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
//Set FWS according to SYS_BOARD_MCKR configuration
EFC0->EEFC_FMR = EEFC_FMR_FWS(4); //4 waitstate flash access
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
// Initialize PLLA to 114MHz
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {}
PMC->PMC_MCKR = SYS_BOARD_MCKR;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
SystemCoreClockUpdate();
pinMode(13, OUTPUT);
noInterrupts();
}
void loop() {
volatile uint32_t i;
digitalWrite(13, HIGH);
for(i=0; i<3500000; ++i) {}
digitalWrite(13, LOW);
for(i=0; i<3500000; ++i) {}
}
The last CPU clock frequency where measured speedup is similar to ideal is 102MHz. Not sure whether factor of 102/84=1.21 that can be achieved with 102MHz is worth the effort of overclocking at all.
Hermann.