I have 6 PCBs being powered in parallel from a 5VDC power supply. When the circuit is not powered, I have checked continuity between the ground pins of the first and last PCB, and the are in fact continuous. But when I power the circuit up, there is a 120mV difference between the ground of the first PCB and the last PCB. What gives??? This is a parallel circuit and the wires are short (less than 2in. between each PCB), shouldn't there be pretty much no difference between the two grounds?
That would be the ideal state.
Perhaps heavier ground wire is needed.
Or bring each ground from a PCB back to the power supply vs daisychaining it thru the boards.
That's exactly what I was thinking. Right now I'm using 22awg wire daisy chaining through the boards. I'm switching to wire each board directly to a 14awg wire branch that runs directly to the power supply, no more daisy chaining.
All this is related to an SPI bus that just won't work properly the further it gets away from the power supply ground. Do you think the difference in ground voltages + the amount of current (and noise) running through each daisy chained PCB is what's screwing with the SPI?
120mV is well within the noise-tolerance of 5V CMOS logic, it
simply won't even notice. Typical 5V logic chips specify 4.5 to 5.5V
or 4.75 to 5.25V, so a 0.12V drop on ground and supply is already
allowed for.
Could just be delay times screwing up the data.
What all do you have connected, and how?
CrossRoads,
This is actually related to another one of my posts that you commented on as well. Here's a link to the post:
http://forum.arduino.cc/index.php?topic=262301.msg1850513#msg1850513
Where do you think the delay might be introduced? Just from the length of the cable? Or from the build-up of shift-out operations on each of the 60 ICs on the bus?
I have a 2 channel oscilloscope, but I'm not sure of the best way to check the synchronization when using the SPI.h library. Calling SPI.transfer() only turns the clock on for the 8 bits, and the delay of subsequent calls to SPI.transfer() (say its in a loop) screws up the scope triggering. Maybe I should just do some manual bit banging to get a more "uniform" clock and data signal going so I can check the sync?
Anyways, I'm still skeptical that it is delay. I was able to get the whole thing to work (even @ 4MHz clock rate) by messing around with the ground wiring. That being said, I'm about halfway done re-wiring the entire power harness. Soon each of the 60 PCBs will be connected directly to the 14awg wire coming straight from the power supply. No more daisy-chaining power through the PCBs... I'm hoping this will better equalize the ground potential for all PCBs, and reduce the amount of current+noise going through the power lines of each PCB.
I did a similar project, needed SCK & SS to go to 45 chips.
I put 9 chips on a card, and a buffer.
Each card buffered SCK & SS for itself and passed it on the next board as well.
Kept the signals clean, and the buffer added only 2-3nS each pass, so total delay added was well within the amount needed to run at 8 MHz (125nS period).
I'll have to look to see what chip I used.
Maybe 74F125.
Yea I've been getting a lot of people pointing me to buffers. The only thing is, I used my oscilloscope to take a look at the CLK and data signals at the far end of the bus and they looked great. Full 5v amplitude, nice sharp rise time with low overshoot/ringing. If my new power routing scheme doesn't work, I'll try buffers next.
Need to get timing measurement of clock edge vs data from chip that is being passed along. May have to write a custom routine that makes it repetitive enough to see it with a 2-channel non-storage scope.
You need a star power and ground wiring not a chained one.
When the circuit is not powered, I have checked continuity between the ground pins of the first and last PCB, and the are in fact continuous. But when I power the circuit up, there is a 120mV difference between the ground of the first PCB and the last PCB.
That is because there is a resistance that you were not measuring correctly when you tested the continuity. You need to measure the resistance and it is a small value but it is finite never the less.
pcdangio:
Yea I've been getting a lot of people pointing me to buffers. The only thing is, I used my oscilloscope to take a look at the CLK and data signals at the far end of the bus and they looked great. Full 5v amplitude, nice sharp rise time with low overshoot/ringing. If my new power routing scheme doesn't work, I'll try buffers next.
What's the sample rate and bandwidth of the 'scope?