My first layout so I'm hoping that I'm on the right track. This design is maybe 80 or 90% there, I just have some decisions to make about what connectors to use on the left edge of the card and board mounting. Otherwise I'm just double checking footprints.
This is the main controller board for my motorcycle digital dash project. Left to right is the power supply and bike input circuitry. Larger traces on bike hookups to try and encourage current loops to stay on that side of the board. In the middle of the board is the main 328 chip that interfaces with bike sensors and the serial connection for the main OLED screen. The 328 to the right is the slave micro that handles infield firmware updates, SD card interface, and up to 2 2row LCD panels. The two are hooked up via hardware SPI with ICSP header inbetween them and a jumper block to set which chip the ICSP header is hooked up to (Moving the jumper from one position to the other disconnects SCK from the main chip, and ties the slave RST to the main RST bus) On the bottom edge of the card is the LCD screen header and contrast adjustment, along with the SD card header, buffer, and 3.3v power. Top right of the card is the button input header, and a superCap to give the controllers time to shut down when the bike is turned off.
10mil typical trace size, with dips to 8 for clearance. Decoupling traces are 20mil with 8mil hookups to main power, again to try and encourage current loops to stay on the decouplers.
My main worries are about keeping interference from noisy bike pickups from causing problems with the board. I'm hoping that the groundplane and keeping all of the noisy incoming lines on the same edge of the board will keep those current loops on that side and away from the rest of the components. Would it be better perhaps to move the power plug (P7) down more towards the rest of the inputs, and have a longer trace feeding the input of the power regulator, but a shorter distance to the main ground hookup for the input circutry?
U6 is 74HC4050, to level shift the datalines to 3.3v for the SD card.
Is this just to allow programming of both CPUs?
Ya. I suppose I could get away with just having the header tied directly into the slave MCU and just using a single jumper to disconnect SCK from the master during programming, but I thought it might be a good idea to be able to break out the headers for either chip, just in case.
The header would still be connected to both tho, since the slaves main purpose is to program the master.
The problem with just switching the SCK is that the slave toggles RST to program the master, so if RST is tied together on both chips it will kill itsself every time the slave starts to program. I also have to make sure that the master is held in reset while the slave is being programmed because the master starts up as an SPI master and would conflict with the programmer.
The 4050 is just a non-inverting hex buffer, but it is tolerant of input voltages above it's own supply.
On power up the slave MCU starts in SPI master mode, holds the master MCU in reset and checks for firmware updates. If there is an update it resets the master MCU's fuse bits, and programs the new code to the chip. When it is done it switches to being an SPI slave and it lets the master startup. From then on it acts as an SPI to 4bit LCD controller and an SD card buffer.
The slave MCUs main purpose is to be an onboard avrISP for the master MCU
If the master MCU is running while the slave MCU is being programmed by an external programmer then both the master MCU and the external programmer will be attempting to assert on the MOSI line at the same time, even if SLK is jumpered to the slave MCU only.
PCB looks pretty good, I'd be inclined to beef up the 5v traces going to the two processors but apart from that I see no glaring problems (of course that doesn't mean there aren't any :))
As for ground loops, I'm pretty shaky on them as well so can't advise there.
A lot of the power traces look thinner than they should be, especially those to U5.
Near P1, try to avoid multiple traces between the pins of the connector. Connector pins tend to be big, and there's not that much room.
Similarly, move the via that's in between pins of P10, and the vias underneath R16 and R17.
On U7, I think it's preferred not to take traces off the "sides" of SMD pads as you've done on the upper left corner.
Can you get rid of the convoluted trace under U4 by using a different gate in the package? If you move the trace that's pulling up the inputs of the unused gates to outside of the package outline, you'll preserve the ability to use them as some sort of re-work.
A trace runs under D5 for no good reason.
The trace that winds its way around the pins of P4 is ugly. It looks like it would move cleanly to the bottom layer.
Spread out the traces that go to P10 from U7. You have plenty of room.
Many of the snaking traces are due to me trying to avoid breaking up the ground plane at all costs, particularly when the the trace is a low power, low speed line (like the one around P4 is a reset line). So perhaps I've just been too stingy with the bottom layer in general?
The trace under D5 is the power tap that feeds the Schmidt trigger, I put it under there to avoid having the extra maybe 1/4" of trace or so to go out between P5 and P8. I was also trying to keep the trace from crossing over the path between P8 and the main ground, since that is the Tach input and is very very noisy. But I suppose it doesn't matter much either way since the current loop for that circuit would really be coming out of the ground via on Q2. Maybe I'd be better off flipping that circuit around so that Q2 is on the outer edge of the board, and feed the power for U4 through a short bottom layer trace right at the top of the chip.
--edit--
Should I just forget about trying to play with impedances on the power traces and just run 20 mil everywhere, or should I just run traces that are wider than they are now (say at U5) but still smaller than the decoupling traces. Like supply trace up from 8mil to 15 mil, with the decoupling trace at 20mil?
I would run big power traces. Even a power plane. If you think you'll need impedence tricks to filter out noise between some sections, add some ferrite bead patterns or something. I don't think that a few mm of narrow trace leading up to the bypass cap is going to make much difference at the frequencies we're talking about here...