peripheral clock enable - uart meaning?

Hi,

I'm reading some code for an mcu. It says 'peripheral clock enable' in a uart configuration. What does the peripheral clock do?

Thanks

ultrasonicbananna: Hi,

I'm reading some code for an mcu. It says 'peripheral clock enable' in a uart configuration. What does the peripheral clock do?

Thanks

I've only seen this terminology used for the XMEGA line of microcontrollers:

Atmel discussion

First:

The sysclk API covers the system clock and all clocks derived from it. The system clock is a chip-internal clock on which all synchronous clocks, i.e. CPU and bus/peripheral clocks, are based. The system clock is typically generated from one of a variety of sources, which may include crystal and RC oscillators as well as PLLs. The clocks derived from the system clock are sometimes also known as synchronous clocks, since they always run synchronously with respect to each other, as opposed to generic clocks which may run from different oscillators or PLLs.

Then:

lfmorrison ... the output of the PLL passes through three divider stages, (one with a division factor defined by PSADIV in the PSCTRL register, and two with division factors defined by PSBCDIV), to produce two high-speed peripheral clocks (one for the high-resolution timer extension, and one for the EBI), and the final CPU clock. The high-speed clock used to drive the high resolution timer is allowed to be up to 4x faster than the main CPU clock, and the EBI clock is allowed to be up to 2x faster than the main CPU clock.