I'm wondering what happens to the state of IO pins when using sleep Power Down mode? For instance if a pull up resistor was on what happens, does the pin mode change, and can it sink current if it was in OUTPUT mode and set to LOW by digitalWrite?
http://www.atmel.com/images/Atmel-8271-8-bit-AVR-Microcontroller-ATmega48A-48PA-88A-88PA-168A-168PA-328-328P_datasheet_Complete.pdf:
In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep Modes for details on which pins are enabled.
Pins configured as outputs stay the way you left them.
Thank you. I read in section 14.2.5 that the internal SLEEP signal grounds the IO pins.
As shown in Figure 14-2, the digital input signal can be clamped to ground at the input of the Schmitt Trigger.
The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save
mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an
analog signal level close to VCC/2
If a pin was issued digitalWrite HIGH command before the power down sleep mode command is issued, what is the result? Is there any way to prevent the pin from being grounded during sleep, or to maintain a high impedance Input or OUTPUT HIGH state?
You understand the quoted part wrong. It does not speak about outside state of the pins:
You can apply "any" voltage on I/O pins. But the when you read the state of the pin from processor you need either HIGH (Vcc) or LOW (GND) even when applied voltage is "somewhere around Vcc/2". So there is "digital buffering" inside the chip to give unambiguous information to the processor. But this digital buffering circuit consumes energy when state of the input pin is close to Vcc/2 or changes between HIGH and LOW. In sleep the processor cannot read the pin state so there is no need to waste energy for digital buffering. So there is switch on the input to the digital buffering circuit - during active state it is connected to its pin. But in sleep it is disconnected from the pin and connected to GND instead to save energy. (It is the same as activate DIDR0 for analog pins.) It has nothing to do with drivers of the pin.
If you were able to digitalRead pins during sleep you would get LOW from all pins (except for pins used for active interrupts). It has nothing to do with output state of the pins - it does not change if the pin is output ot input and if it is HIGH or LOW - basicly there is no way to determine if processor is asleep by reading pins.
I found that the external portion of pins terminate at a transmission gate device. In the schematic the symbol is the one that looks like 4 triangles (see attached pictures from 328p datasheet page 80).
I found what it was by doing a Google image search and found this forum post right away: What is this quadruple triangle logic symbol? - Electrical Engineering Stack Exchange
As I understand it, the external pin is completely disconnected from the MCU by the transmission gate when Power Down sleep mode is activated as well as some other sleep modes. Thus the pin cannot be in any state determined by the MCU, it is simply an "air wire" at that point. Is this correct?
Only input to MCU is disconnected. Output drivers are still connected and active if they were activated by their register bits.
You are correct, I was focussing on the input logic circuit and missed the upper portion of the diagram with the driver circuits. According the 328p datasheet:
10.10.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is
then to ensure that no pins drive resistive loads.
This indicates / supports the fact that the pin driver circuits are not effected during sleep and thus pins should behave during sleep the same as they did before sleep; source or sink current, maintain a OUTPUT HIGH, OUTPUT LOW, INPUT, or INPUT_PULLUP state. Is this correct?
Yes.