PIO_PDSR Speed according to graph


I am not quite sure if I interpret this graph correctly. Does it mean that PIO_PDSR needs 5 clock cycles to read the Pin Status and thus is able to read at 84MHz/5 = 16.8MHz max?

The picture you included is for output...
I don't see an exact duplicate (ie one that includes APB access time) for input. And it could be more pipeline (latency) rather than max read rate.
Don't forget flash wait states (probably not very deterministic.)

To find an average of clock cycle need to read PIO_PDSR, you could use the below sketch (add SysTick->VAL to read clock cycle number to the sketch):

/*     Find an average of PIO_PDSR clock cycle number  */

void setup() {


void loop() {

  uint32_t t0, t1, t3;
  register uint32_t __A asm ("r0");
  uint8_t A_Size = 4;
  uint32_t A[A_Size];
  uint8_t Index;
  // Use SysTick from here....
  __A += PIOD->PIO_PDSR;
  __A += PIOD->PIO_PDSR;
  __A += PIOD->PIO_PDSR;
  A[Index] = __A;
  // .... to here.

  // To be sure PIO_PDSR is effectively logged
  for (Index = A_Size; Index>0;--Index) {
   Serial.println(A[Index], BIN);

 // Serial print clock cycle number divided by A_Size