The thing is that these two interrupts are running asynchronously. So you have to consider what will happen when they go off at exactly the same time, or very close together and which is the more important for you. So if the ADC one goes off just a fraction before the timer then that ISR will be running when the timer interrupt goes off. Clearing the interrupt in the ADC ISR will allow the timer to interrupt the ADC ISR. So an ISR is interrupted by another ISR which has a higher priority.
Some processors allow you to select the order of priority of ISRs but the ATmega is not one of these, so you have to resort to other tricks like this.
When the timer ISR returns, it will return to the ADC ISR which will then be vulnerable to being interrupted again. But when this returns everything is back to normal.
You won't notice this every time or even at all if the delay is very small, but in real time computing like this you have to consider all possibilities of what could happen and when.