For the power up and down cycle of this IC (HV507) it states to connect and/or disconnect the ground. Plus remove the inputs and power supplies.
For the power supplies I would assume this would just mean turn them off.
For the inputs, I would assume this would mean just turning those off, or set them all LOW.
But why would I connect/disconnect the ground? I assume I would have to perform this using a relay?
Any help would be appreciated. HV507 datasheet, table 3.1 shows these details.
I’ve had a look at table 3.1 and ... seems strange ! ( although I’ve not understood in detail what the chip does )
Think I would look for some application examples ( google) to how people use it, seems an odd device to want to use - whats you project ??
Not strange at all. The internal latches must all be set before high voltage is applied to them. Makes sense, doesn't it?
Same applies to shut down. Remove all high voltage connections while latches are set and then power down the internal latches.
All equipment using a mix low voltages and high voltages do or should do the same order.
As far as I see, this does not mean that, in normal operation, you have to ever disconnect ground. It simply means never apply voltage(s) to the device without ground being connected.
What, incidentally, are going to use this chip for? The maximum high voltage current is very low.
The chip has separate GND and HVGND, the table 3.1 is unclear but I suspect its only talking about HVGND.
I see the Mouser datasheet for the device is a bit older that the one on the Microchip site. It is slightly less explicit about the power off sequence. It is not clear whether new engineering input has flown into this document or only "corporate identity" features and rewording.
Anyway, I found this schematic where the HV507 is used in a design.
The full project is here. The grounds in this design appears to be common to the logic and high voltage side. Maybe you can use parts of this design.
Ah okay. So I think what we are agreeing on here, is that the main point the sequencing table is talking about, is that Vdd should be on before Vpp (low voltage before high). Making sure GND is always connected. Thanks all
I'd just add the caveat that if you are making the grounds common, then that should be so.
However, neither datasheet (Supertex nor Microchip) is not very clear on what happens when the ground potentials are not the same or how far they may diverge. That would also be interesting information.
I will be connecting both grounds I think
The fact that is says, connect ground, rather than both, or an individual one, implies that they are both connected.
Would anyone have hardware ideas on how to build a cct that turns off the 160V+ before the 5V? As the power down dequence suggests?
Would a bunch of suppression caps on the 5V output and none on the 160V+ output be sufficient to keep the 5V high for long enough?
It is very low current you are switching. For a similar application, that is switching the high voltage from a Nixie tube power supply, I use an opto coupler TLP387. That can be driven from a 3.3 volt pin (with only a suitable series resistor)
I don't like the sound of that. If you want to switch 5 volts, use a transistor (or mosfet).
I am just trying to get my head around:
12V input, goes to 5V regulator for low level voltage and goes to a 160V boost for this IC.
If the whole cct looses the 12V in for example, how best could I design a cct so that the 5V regulator keep a little juice for longer than the 160V - meeting the power down sequence requirements of the datasheet?
OK. Then describe how you have designed the timings of the power switching in normal operation before considering the edge case of a power failure.
For example, have you got the 160v boost converter switched somehow via an Arduino GPIO pin so that it starts a few seconds after the 5 volt supply becomes available ? And, perhaps, the reverse, in a controlled shutdown, where the boost converter is switched off some time before the power supply /supplies are unlatched ?
Boost the 160V from the 5V rail perhaps? But another possibility is to high-side switch the 160V actively - perhaps a comparator detects if the 5V rail is dropping and
disconnects the 160V.
Or you simply arrange a much longer time constant for the 5V rail's decoupling.
I like the compatator idea. Something for me to try and figure out. Thanks Mark.
I've tried simulating this on LTspice... but not had much success. I've just tried varying the capacitance of a decoupling cap, and the discharging curve doesnt seem to show. Is this just a simulation error maybe? In my head, the discharge rate would be t=RC, so do I need a series resistance coming off both my 5V and 160V rails to create the characteristic discharge curve please?
Current idea: use an opto coupler like stated above to turn the HV in to that IC off when 12V is removed. Then it will definately be removed before the 5V rail caps discharge.
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