Agreed, in an ideal world I'd have the main module make that request / announcement via the rs485 bus and be done with it. However, if the main CPU is occupied trying to transmit something via GPRS (with its delays, etc) then maintaining the timing signal accuracy might become difficult.
So a quad buffer chip might be a better solution. One wire communicates the timing signal, the other reserves the use of the rs485 bus. Or, I skip bus reservations and use the pair solely to xmit the timing signal. I'd have to make the slaves a little smarter but nothing impossible, I reckon.