Problem uploading sketch in verify phase

This is very strange. Today I repeated exactly the same procedure to reproduce the error. And now it works correctly.
I have tried with the verbose turned on and off in both the compile and upload options, no difference. If the issue shows up again as I strongly suspect it will, I will try to capture the output of the dialog and post it here. BTW, I now have the 8mhz bootloader at 57600 installed, I will try putting back the 16mhz bootloader at 115200 and replace the 16mhz crystal and try it again. I have two options in boards.txt one for each case. (It's possible a final product will use a processor running at 3.3v to be compatible with other LV parts hence having the 8mhz development option).