Your sketch says:
#define M_S0 7
#define M_S1 6
#define M_S2 5
#define S_S0 2
#define S_S1 3
#define S_S2 4
Your schematic seems to show:
Pin 5 -> Master A (pin 11, S0, LSB)
Pin 6 -> Master B (pin 10, S1)
Pin 7 -> Master C (pin 9, S2, MSB)
Pin 8 -> Slave A (pin 11, S0, LSB)
Pin 9 -> Slave B (pin 10, S1)
Pin 10 -> Slave C (pin 9, S2, MSB)
The only pin that matches is Pin 6 -> Master B / Master pin 10 / Master S1 so they can't both be correct.