Can I see your code for your application? I'm trying to understand how the daisy-chaining is supposed to work.
From the data-sheet:
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
I'm not sure how having one chain of 8 modules and one of 9 modules can be programmed identically (but I suppose the last module in the chain of 8 can output to 'nothing').
Your 2 chains are 'working' in parallel correct?